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Commit e9862118 authored by Shunli Wang's avatar Shunli Wang Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT2701 clock support 



Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: default avatarShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: default avatarErin Lo <erin.lo@mediatek.com>
Tested-by: default avatarJohn Crispin <blogic@openwrt.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent e0a3862c

drivers/clk/mediatek/Kconfig

+43 −0
Original line number Diff line number Diff line
@@ -6,6 +6,49 @@ config COMMON_CLK_MEDIATEK 
	---help---

	  Mediatek SoCs' clock support.



config COMMON_CLK_MT2701

	bool "Clock driver for Mediatek MT2701"

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	---help---

	  This driver supports Mediatek MT2701 basic clocks.



config COMMON_CLK_MT2701_MMSYS

	bool "Clock driver for Mediatek MT2701 mmsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 mmsys clocks.



config COMMON_CLK_MT2701_IMGSYS

	bool "Clock driver for Mediatek MT2701 imgsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 imgsys clocks.



config COMMON_CLK_MT2701_VDECSYS

	bool "Clock driver for Mediatek MT2701 vdecsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 vdecsys clocks.



config COMMON_CLK_MT2701_HIFSYS

	bool "Clock driver for Mediatek MT2701 hifsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 hifsys clocks.



config COMMON_CLK_MT2701_ETHSYS

	bool "Clock driver for Mediatek MT2701 ethsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 ethsys clocks.



config COMMON_CLK_MT2701_BDPSYS

	bool "Clock driver for Mediatek MT2701 bdpsys"

	select COMMON_CLK_MT2701

	---help---

	  This driver supports Mediatek MT2701 bdpsys clocks.



config COMMON_CLK_MT8135

	bool "Clock driver for Mediatek MT8135"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+7 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o

obj-$(CONFIG_RESET_CONTROLLER) += reset.o

obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o

obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o

obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o

obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o

obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o

obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o

obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o

obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o

obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

drivers/clk/mediatek/clk-gate.c

+52 −0
Original line number Diff line number Diff line
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw) 
	regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));

}



static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)

{

	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);

	u32 cgbit = BIT(cg->bit);



	regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);

}



static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)

{

	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);

	u32 cgbit = BIT(cg->bit);



	regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);

}



static int mtk_cg_enable(struct clk_hw *hw)

{

	mtk_cg_clr_bit(hw);
@@ -85,6 +101,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw) 
	mtk_cg_clr_bit(hw);

}



static int mtk_cg_enable_no_setclr(struct clk_hw *hw)

{

	mtk_cg_clr_bit_no_setclr(hw);



	return 0;

}



static void mtk_cg_disable_no_setclr(struct clk_hw *hw)

{

	mtk_cg_set_bit_no_setclr(hw);

}



static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)

{

	mtk_cg_set_bit_no_setclr(hw);



	return 0;

}



static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)

{

	mtk_cg_clr_bit_no_setclr(hw);

}



const struct clk_ops mtk_clk_gate_ops_setclr = {

	.is_enabled	= mtk_cg_bit_is_cleared,

	.enable		= mtk_cg_enable,
@@ -97,6 +137,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = { 
	.disable	= mtk_cg_disable_inv,

};



const struct clk_ops mtk_clk_gate_ops_no_setclr = {

	.is_enabled	= mtk_cg_bit_is_cleared,

	.enable		= mtk_cg_enable_no_setclr,

	.disable	= mtk_cg_disable_no_setclr,

};



const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {

	.is_enabled	= mtk_cg_bit_is_set,

	.enable		= mtk_cg_enable_inv_no_setclr,

	.disable	= mtk_cg_disable_inv_no_setclr,

};



struct clk *mtk_clk_register_gate(

		const char *name,

		const char *parent_name,

drivers/clk/mediatek/clk-gate.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) 


extern const struct clk_ops mtk_clk_gate_ops_setclr;

extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;

extern const struct clk_ops mtk_clk_gate_ops_no_setclr;

extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;



struct clk *mtk_clk_register_gate(

		const char *name,

drivers/clk/mediatek/clk-mt2701-bdp.c

0 → 100644
+138 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014 MediaTek Inc.

 * Author: Shunli Wang <shunli.wang@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt2701-clk.h>



static const struct mtk_gate_regs bdp0_cg_regs = {

	.set_ofs = 0x0104,

	.clr_ofs = 0x0108,

	.sta_ofs = 0x0100,

};



static const struct mtk_gate_regs bdp1_cg_regs = {

	.set_ofs = 0x0114,

	.clr_ofs = 0x0118,

	.sta_ofs = 0x0110,

};



#define GATE_BDP0(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &bdp0_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr_inv,	\

	}



#define GATE_BDP1(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &bdp1_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr_inv,	\

	}



static const struct mtk_gate bdp_clks[] = {

	GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),

	GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),

	GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),

	GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),

	GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),

	GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),

	GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),

	GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),

	GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),

	GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),

	GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),

	GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),

	GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),

	GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),

	GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),

	GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),

	GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),

	GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),

	GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),

	GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),

	GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),

	GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),

	GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),

	GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),

	GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),

	GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),

	GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),

	GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),

	GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),

	GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),

	GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),

	GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),

	GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),

	GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),

	GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),

	GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),

	GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),

	GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),

	GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),

	GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),

	GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),

	GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),

	GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),

	GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),

	GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),

	GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),

	GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),

	GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),

	GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),

};



static const struct of_device_id of_match_clk_mt2701_bdp[] = {

	{ .compatible = "mediatek,mt2701-bdpsys", },

	{}

};



static int clk_mt2701_bdp_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_BDP_NR);



	mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),

						clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	return r;

}



static struct platform_driver clk_mt2701_bdp_drv = {

	.probe = clk_mt2701_bdp_probe,

	.driver = {

		.name = "clk-mt2701-bdp",

		.of_match_table = of_match_clk_mt2701_bdp,

	},

};



builtin_platform_driver(clk_mt2701_bdp_drv);