Loading arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi +32 −32 Original line number Diff line number Diff line Loading @@ -217,37 +217,37 @@ msi-controller; reg = <0x17a00040 0x0>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 711 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 712 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 714 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 716 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 719 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 720 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 721 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 722 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 723 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 724 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 725 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 726 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 727 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 728 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 729 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 730 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 731 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 732 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 733 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 734 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 735 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 736 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 737 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 738 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 739 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 740 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 741 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 672 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 673 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 674 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 675 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 676 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 683 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 684 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 685 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 686 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 687 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 689 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 690 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 691 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 692 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 693 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 694 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 695 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 696 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 697 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 701 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>; }; }; Loading
arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi +32 −32 Original line number Diff line number Diff line Loading @@ -217,37 +217,37 @@ msi-controller; reg = <0x17a00040 0x0>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 711 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 712 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 714 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 716 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 719 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 720 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 721 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 722 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 723 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 724 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 725 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 726 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 727 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 728 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 729 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 730 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 731 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 732 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 733 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 734 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 735 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 736 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 737 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 738 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 739 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 740 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 741 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 672 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 673 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 674 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 675 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 676 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 683 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 684 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 685 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 686 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 687 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 689 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 690 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 691 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 692 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 693 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 694 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 695 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 696 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 697 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 701 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>; }; };