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Commit e9002f7b authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: dispcc: Add 172MHz frequency support for SDMMAGPIE 



Derive a frequency of 172MHz from dispcc PLL0 and also add the set rate
flag so as to propagate the GPLL0 rate to "gcc_disp_gpll0_clk_src".

Change-Id: I075652733748a7bc9ead70aac23ec6e381775af4
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 51683be8

drivers/clk/qcom/dispcc-sdmmagpie.c

+2 −1
Original line number Diff line number Diff line
@@ -415,7 +415,7 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 
	F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),

	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),

	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),

	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),

	F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 5, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),

	F(286666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),

	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
@@ -435,6 +435,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 
		.name = "disp_cc_mdss_mdp_clk_src",

		.parent_names = disp_cc_parent_names_3,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,