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Commit e8f9bb1b authored by Nicolas Pitre's avatar Nicolas Pitre
Browse files

ARM: vexpress/dcscb: fix cache disabling sequences 



Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: default avatarNicolas Pitre <nico@linaro.org>
parent 3b2f64d0

arch/arm/mach-vexpress/dcscb.c

+37 −21
Original line number Original line Diff line number Diff line
@@ -136,14 +136,29 @@ static void dcscb_power_down(void) 
		/*

		/*

		 * Flush all cache levels for this cluster.

		 * Flush all cache levels for this cluster.

		 *

		 *

		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need

		 * To do so we do:

		 * a preliminary flush here for those CPUs.  At least, that's

		 * - Clear the SCTLR.C bit to prevent further cache allocations

		 * the theory -- without the extra flush, Linux explodes on

		 * - Flush the whole cache

		 * RTSM (to be investigated).

		 * - Clear the ACTLR "SMP" bit to disable local coherency

		 *

		 * Let's do it in the safest possible way i.e. with

		 * no memory access within the following sequence

		 * including to the stack.

		 */

		 */

		flush_cache_all();

		asm volatile(

		set_cr(get_cr() & ~CR_C);

		"mrc	p15, 0, r0, c1, c0, 0	@ get CR \n\t"

		flush_cache_all();

		"bic	r0, r0, #"__stringify(CR_C)" \n\t"

		"mcr	p15, 0, r0, c1, c0, 0	@ set CR \n\t"

		"isb	\n\t"

		"bl	v7_flush_dcache_all \n\t"

		"clrex	\n\t"

		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR \n\t"

		"bic	r0, r0, #(1 << 6)	@ disable local coherency \n\t"

		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR \n\t"

		"isb	\n\t"

		"dsb	"

		: : : "r0","r1","r2","r3","r4","r5","r6","r7",

		      "r9","r10","r11","lr","memory");





		/*

		/*

		 * This is a harmless no-op.  On platforms with a real

		 * This is a harmless no-op.  On platforms with a real
@@ -152,9 +167,6 @@ static void dcscb_power_down(void) 
		 */

		 */

		outer_flush_all();

		outer_flush_all();





		/* Disable local coherency by clearing the ACTLR "SMP" bit: */

		set_auxcr(get_auxcr() & ~(1 << 6));



		/*

		/*

		 * Disable cluster-level coherency by masking

		 * Disable cluster-level coherency by masking

		 * incoming snoops and DVM messages:

		 * incoming snoops and DVM messages:
@@ -167,18 +179,22 @@ static void dcscb_power_down(void) 




		/*

		/*

		 * Flush the local CPU cache.

		 * Flush the local CPU cache.

		 *

		 * Let's do it in the safest possible way as above.

		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need

		 * a preliminary flush here for those CPUs.  At least, that's

		 * the theory -- without the extra flush, Linux explodes on

		 * RTSM (to be investigated).

		 */

		 */

		flush_cache_louis();

		asm volatile(

		set_cr(get_cr() & ~CR_C);

		"mrc	p15, 0, r0, c1, c0, 0	@ get CR \n\t"

		flush_cache_louis();

		"bic	r0, r0, #"__stringify(CR_C)" \n\t"



		"mcr	p15, 0, r0, c1, c0, 0	@ set CR \n\t"

		/* Disable local coherency by clearing the ACTLR "SMP" bit: */

		"isb	\n\t"

		set_auxcr(get_auxcr() & ~(1 << 6));

		"bl	v7_flush_dcache_louis \n\t"

		"clrex	\n\t"

		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR \n\t"

		"bic	r0, r0, #(1 << 6)	@ disable local coherency \n\t"

		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR \n\t"

		"isb	\n\t"

		"dsb	"

		: : : "r0","r1","r2","r3","r4","r5","r6","r7",

		      "r9","r10","r11","lr","memory");

	}

	}





	__mcpm_cpu_down(cpu, cluster);

	__mcpm_cpu_down(cpu, cluster);