Loading drivers/usb/dwc3/core.c +7 −0 Original line number Diff line number Diff line Loading @@ -933,6 +933,13 @@ int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } /* set inter-packet gap 199.794ns to improve EL_23 margin */ if (dwc->revision >= DWC3_USB31_REVISION_170A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); reg |= DWC3_GUCTL1_IP_GAP_ADD_ON(1); dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } return 0; err3: Loading drivers/usb/dwc3/core.h +1 −0 Original line number Diff line number Diff line Loading @@ -221,6 +221,7 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) #define DWC3_GUCTL1_IP_GAP_ADD_ON(n) (n << 21) /* Global Debug LTSSM Register */ #define DWC3_GDBGLTSSM_LINKSTATE_MASK (0xF << 22) Loading Loading
drivers/usb/dwc3/core.c +7 −0 Original line number Diff line number Diff line Loading @@ -933,6 +933,13 @@ int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } /* set inter-packet gap 199.794ns to improve EL_23 margin */ if (dwc->revision >= DWC3_USB31_REVISION_170A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); reg |= DWC3_GUCTL1_IP_GAP_ADD_ON(1); dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } return 0; err3: Loading
drivers/usb/dwc3/core.h +1 −0 Original line number Diff line number Diff line Loading @@ -221,6 +221,7 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) #define DWC3_GUCTL1_IP_GAP_ADD_ON(n) (n << 21) /* Global Debug LTSSM Register */ #define DWC3_GDBGLTSSM_LINKSTATE_MASK (0xF << 22) Loading