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Commit e87c4699 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
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agp/intel: allow cacheable and GDFT PTEs on ValleyView 



The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.

Note: I have my questions whether this is right, given that MLC died
for snb & ivb, that ivb has grown a L3$ cache instead (which vlv seems
to have, too) and that the LLC bit here isn't actually LLC, but just
means 'snoop cpu caches'.

But I plan to burn this all with the heat of a thousands suns in my
gtt rework, so who cares ;-)

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Added note.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bd9e8413

drivers/char/agp/intel-gtt.c

+9 −2
Original line number Diff line number Diff line
@@ -1183,9 +1183,17 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 
static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,

				   unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;

	else {

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;
@@ -1380,7 +1388,6 @@ static const struct intel_gtt_driver valleyview_gtt_driver = { 
	.write_entry = valleyview_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};



/* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of