Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (e86137b2) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi

+0 −1

Original line number	Diff line number	Diff line
		@@ -29,7 +29,6 @@
		qcom,mdss-dsi-lane-1-state;
		qcom,mdss-dsi-lane-2-state;
		qcom,mdss-dsi-lane-3-state;
		qcom,cmd-sync-wait-broadcast;
		qcom,mdss-dsi-dma-trigger = "trigger_sw";
		qcom,mdss-dsi-mdp-trigger = "none";
		qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+30 −2

Original line number	Diff line number	Diff line
		@@ -430,6 +430,13 @@
		qcom,mdss-dsi-max-refresh-rate = <60>;
		qcom,mdss-dsi-pan-enable-dynamic-fps;
		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-on-check-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -461,6 +468,13 @@
		};

		&dsi_nt35597_truly_dsc_cmd {
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-on-check-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
		@@ -474,6 +488,13 @@
		};

		&dsi_nt35597_truly_dsc_video {
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-on-check-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
		@@ -487,6 +508,13 @@
		};

		&dsi_sharp_4k_dsc_video {
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
		qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
		qcom,mdss-dsi-panel-status-value = <0x77>;
		qcom,mdss-dsi-panel-on-check-value = <0x77>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
		@@ -502,8 +530,8 @@
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x7>;
		qcom,mdss-dsi-panel-on-check-value = <0x7>;
		qcom,mdss-dsi-panel-status-value = <0x77>;
		qcom,mdss-dsi-panel-on-check-value = <0x77>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -925,6 +925,11 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw,
		if (!vco->priv)
		pr_err("vco priv is null\n");

		if (!pll) {
		pr_err("pll is null\n");
		return 0;
		}

		/*
		* Calculate the vco rate from HW registers only for handoff cases.
		* For other cases where a vco_10nm_set_rate() has already been

drivers/gpu/drm/msm/dp/dp_catalog.c

+52 −0

Original line number	Diff line number	Diff line
		@@ -1573,6 +1573,57 @@ static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
		dp_write(catalog, io_data, DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
		}

		static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
		u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
		{
		struct dp_catalog_private *catalog;
		struct dp_io_data *io_data = NULL;
		u32 i, slot_reg_1, slot_reg_2, slot;
		u32 reg_off = 0;

		if (!ctrl \|\| ch >= DP_STREAM_MAX) {
		pr_err("invalid input. ch %d\n", ch);
		return;
		}

		if (ch_start_slot > DP_MAX_TIME_SLOTS \|\|
		(ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
		pr_err("invalid slots start %d, tot %d\n",
		ch_start_slot, tot_slot_cnt);
		return;
		}

		catalog = dp_catalog_get_priv(ctrl);

		io_data = catalog->io.dp_link;

		pr_debug("dealloc ch %d, start_slot %d, tot_slot %d\n",
		ch, ch_start_slot, tot_slot_cnt);

		if (ch == DP_STREAM_1)
		reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;

		slot_reg_1 = dp_read(catalog, io_data, DP_DP0_TIMESLOT_1_32 + reg_off);
		slot_reg_2 = dp_read(catalog, io_data, DP_DP0_TIMESLOT_33_63 + reg_off);

		ch_start_slot = ch_start_slot - 1;
		for (i = 0; i < tot_slot_cnt; i++) {
		if (ch_start_slot < 33) {
		slot_reg_1 &= ~BIT(ch_start_slot);
		} else {
		slot = ch_start_slot - 33;
		slot_reg_2 &= ~BIT(slot);
		}
		ch_start_slot++;
		}

		pr_debug("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
		slot_reg_1, slot_reg_2);

		dp_write(catalog, io_data, DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
		dp_write(catalog, io_data, DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
		}

		static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
		u32 x_int, u32 y_frac_enum)
		{
		@@ -2111,6 +2162,7 @@ struct dp_catalog dp_catalog_get(struct device dev, struct dp_parser *parser)
		.read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
		.channel_alloc = dp_catalog_ctrl_channel_alloc,
		.update_rg = dp_catalog_ctrl_update_rg,
		.channel_dealloc = dp_catalog_ctrl_channel_dealloc,
		};
		struct dp_catalog_audio audio = {
		.init = dp_catalog_audio_init,

drivers/gpu/drm/msm/dp/dp_catalog.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,8 @@ struct dp_catalog_ctrl {
		u32 ch, u32 ch_start_timeslot, u32 tot_ch_cnt);
		void (update_rg)(struct dp_catalog_ctrl ctrl, u32 ch, u32 x_int,
		u32 y_frac_enum);
		void (channel_dealloc)(struct dp_catalog_ctrl ctrl,
		u32 ch, u32 ch_start_timeslot, u32 tot_ch_cnt);
		};

		#define HEADER_BYTE_2_BIT 0