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Commit e860130f authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: gpucc: Update the frequencies for GFX3D clock 



The GFX3d clock frequencies have been updated and also the fmax corners, so
update the same.

Change-Id: I9ec1e034ccf33d4d464c91936128df6195558c2a
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 5fea65c1

drivers/clk/qcom/gpucc-sdmmagpie.c

+43 −4
Original line number Diff line number Diff line
@@ -183,6 +183,42 @@ static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { 
	},

};



static struct clk_alpha_pll gpu_cc_pll1 = {

	.offset = 0x100,

	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_pll1",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_fabia_pll_ops,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_even = {

	.offset = 0x100,

	.post_div_shift = 8,

	.post_div_table = post_div_table_fabia_even,

	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),

	.width = 4,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_pll1_out_even",

		.parent_names = (const char *[]){ "gpu_cc_pll1" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_generic_pll_postdiv_ops,

	},

};

static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
@@ -216,8 +252,8 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { 
	F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(780000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(800000000, P_GPU_CC_PLL1_OUT_EVEN, 2, 0, 0),

	F(825000000, P_GPU_CC_PLL1_OUT_EVEN, 2, 0, 0),

	{ }

};
@@ -243,8 +279,8 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { 
			[VDD_GX_LOW_L1] = 430000000,

			[VDD_GX_NOMINAL] = 565000000,

			[VDD_GX_NOMINAL_L1] = 650000000,

			[VDD_GX_HIGH] = 750000000,

			[VDD_GX_HIGH_L1] = 780000000},

			[VDD_GX_HIGH] = 800000000,

			[VDD_GX_HIGH_L1] = 825000000},

	},

};
@@ -488,6 +524,8 @@ static struct clk_regmap *gpu_cc_sdmmagpie_clocks[] = { 
	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,

	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,

	[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,

	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,

	[GPU_CC_PLL1_OUT_EVEN] = &gpu_cc_pll1_out_even.clkr,

};



static const struct regmap_config gpu_cc_sdmmagpie_regmap_config = {
@@ -552,6 +590,7 @@ static int gpu_cc_sdmmagpie_probe(struct platform_device *pdev) 
	}



	clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);

	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll0_config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sdmmagpie_desc, regmap);

	if (ret) {

include/dt-bindings/clock/qcom,gpucc-sdmmagpie.h

+20 −18
Original line number Diff line number Diff line
@@ -16,23 +16,25 @@ 


#define GPU_CC_PLL0						0

#define GPU_CC_PLL0_OUT_EVEN					1

#define GPU_CC_ACD_AHB_CLK					2

#define GPU_CC_ACD_CXO_CLK					3

#define GPU_CC_AHB_CLK						4

#define GPU_CC_CRC_AHB_CLK					5

#define GPU_CC_CX_APB_CLK					6

#define GPU_CC_CX_GFX3D_CLK					7

#define GPU_CC_CX_GFX3D_SLV_CLK					8

#define GPU_CC_CX_GMU_CLK					9

#define GPU_CC_CX_SNOC_DVM_CLK					10

#define GPU_CC_CXO_AON_CLK					11

#define GPU_CC_CXO_CLK						12

#define GPU_CC_GMU_CLK_SRC					13

#define GPU_CC_GX_CXO_CLK					14

#define GPU_CC_GX_GFX3D_CLK					15

#define GPU_CC_GX_GFX3D_CLK_SRC					16

#define GPU_CC_GX_GMU_CLK					17

#define GPU_CC_GX_VSENSE_CLK					18

#define GPU_CC_SLEEP_CLK					19

#define GPU_CC_PLL1						2

#define GPU_CC_PLL1_OUT_EVEN					3

#define GPU_CC_ACD_AHB_CLK					4

#define GPU_CC_ACD_CXO_CLK					5

#define GPU_CC_AHB_CLK						6

#define GPU_CC_CRC_AHB_CLK					7

#define GPU_CC_CX_APB_CLK					8

#define GPU_CC_CX_GFX3D_CLK					9

#define GPU_CC_CX_GFX3D_SLV_CLK					10

#define GPU_CC_CX_GMU_CLK					11

#define GPU_CC_CX_SNOC_DVM_CLK					12

#define GPU_CC_CXO_AON_CLK					13

#define GPU_CC_CXO_CLK						14

#define GPU_CC_GMU_CLK_SRC					15

#define GPU_CC_GX_CXO_CLK					16

#define GPU_CC_GX_GFX3D_CLK					17

#define GPU_CC_GX_GFX3D_CLK_SRC					18

#define GPU_CC_GX_GMU_CLK					19

#define GPU_CC_GX_VSENSE_CLK					20

#define GPU_CC_SLEEP_CLK					21



#endif