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Commit e840c13d authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add USB PHYs configuration on sdxprairie"

parents 0c692d7a 078e4bb4

arch/arm64/boot/dts/qcom/sdxprairie-rumi.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -73,3 +73,11 @@ 
		maximum-speed = "high-speed";

	};

};



&usb_qmp_phy {

	status = "disabled";

};



&usb2_phy {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi

+153 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include <dt-bindings/clock/qcom,gcc-sdxprairie.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/phy/qcom,sdxprairie-qmp-usb3.h>



&soc {

	usb: ssusb@a600000 {
@@ -78,6 +79,7 @@ 
			compatible = "snps,dwc3";

			reg = <0x0a600000 0xcd00>;

			interrupts = <0 133 0>;

			usb-phy = <&usb2_phy>, <&usb_qmp_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;
@@ -123,4 +125,155 @@ 
	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};



	usb2_phy: hsphy@ff4000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0xff4000 0x114>;

		reg-names = "hsusb_phy_base";



		vdd-supply = <&pmxprairie_l4>;

		qcom,vdd-voltage-level = <0 872000 872000>;

		vdda18-supply = <&pmxprairie_l5>;

		vdda33-supply = <&pmxprairie_l10>;



		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

		clock-names = "ref_clk_src", "cfg_ahb_clk";



		resets = <&clock_gcc GCC_QUSB2PHY_BCR>;

		reset-names = "phy_reset";

	};



	usb_qmp_phy: ssphy@ff6000 {

		compatible = "qcom,usb-ssphy-qmp-v2";

		reg = <0xff6000 0x1000>,

			<0xff688c 0x4>;

		reg-names = "qmp_phy_base",

			"pcs_clamp_enable_reg";



		vdd-supply = <&pmxprairie_l4>;

		qcom,vdd-voltage-level = <0 872000 872000>;

		qcom,vdd-max-load-uA = <47900>;

		core-supply = <&pmxprairie_l1>;

		qcom,core-max-load-uA = <15000>;

		qcom,vbus-valid-override;

		qcom,qmp-phy-init-seq =

		    /* <reg_offset, value, delay> */

		    <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

		     USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0

		     USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

		     USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0

		     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

		     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

		     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

		     USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0

		     USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

		     USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

		     USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

		     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

		     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

		     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

		     USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0

		     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0

		     USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0

		     USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xef 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0

		     USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0

		     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0

		     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0

		     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0

		     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0

		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0

		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0

		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0

		     USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0

		     USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0

		     USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

		     USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0

		     USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0

		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0

		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0

		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x05 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

		     USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0

		     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0

		     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

		     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

		     USB3_UNI_PCS_CDR_RESET_TIME 0x0f 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_UNI_PCS_EQ_CONFIG1 0x4b 0

		     USB3_UNI_PCS_EQ_CONFIG5 0x10 0

		     USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0

		     0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

				<USB3_UNI_PCS_PCS_STATUS1

				 USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL

				 USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR

				 USB3_UNI_PCS_POWER_DOWN_CONTROL

				 USB3_UNI_PCS_SW_RESET

				 USB3_UNI_PCS_START_CONTROL>;



		clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,

			 <&clock_gcc GCC_USB3_PHY_PIPE_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",

				"cfg_ahb_clk";



		resets = <&clock_gcc GCC_USB3_PHY_BCR>,

			<&clock_gcc GCC_USB3PHY_PHY_BCR>;

		reset-names = "phy_reset", "phy_phy_reset";

	};

};

include/dt-bindings/phy/qcom,sdxprairie-qmp-usb3.h

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