Merge "Merge remote-tracking branch 'remotes/origin/tmp-f2e8962' into msm-4.14" (e6de4497) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/x86/pti.txt

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -78,7 +78,7 @@ this protection comes at a cost:
	non-PTI SYSCALL entry code, so requires mapping fewer		non-PTI SYSCALL entry code, so requires mapping fewer
	things into the userspace page tables. The downside is		things into the userspace page tables. The downside is
	that stacks must be switched at entry time.		that stacks must be switched at entry time.
	d. Global pages are disabled for all kernel structures not		c. Global pages are disabled for all kernel structures not
	mapped into both kernel and userspace page tables. This		mapped into both kernel and userspace page tables. This
	feature of the MMU allows different processes to share TLB		feature of the MMU allows different processes to share TLB
	entries mapping the kernel. Losing the feature means more		entries mapping the kernel. Losing the feature means more

Makefile

+1 −1

Original line number	Original line	Diff line number	Diff line
	# SPDX-License-Identifier: GPL-2.0		# SPDX-License-Identifier: GPL-2.0
	VERSION = 4		VERSION = 4
	PATCHLEVEL = 14		PATCHLEVEL = 14
	SUBLEVEL = 14		SUBLEVEL = 15
	EXTRAVERSION =		EXTRAVERSION =
	NAME = Petit Gorille		NAME = Petit Gorille

arch/alpha/kernel/sys_sio.c

+29 −6

Original line number	Original line	Diff line number	Diff line
	@@ -102,6 +102,15 @@ sio_pci_route(void)
	alpha_mv.sys.sio.route_tab);		alpha_mv.sys.sio.route_tab);
	}		}

			static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
			{
			if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
			(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
			return false;

			return true;
			}

	static unsigned int __init		static unsigned int __init
	sio_collect_irq_levels(void)		sio_collect_irq_levels(void)
	{		{
	@@ -110,8 +119,7 @@ sio_collect_irq_levels(void)

	/* Iterate through the devices, collecting IRQ levels. */		/* Iterate through the devices, collecting IRQ levels. */
	for_each_pci_dev(dev) {		for_each_pci_dev(dev) {
	if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&		if (!sio_pci_dev_irq_needs_level(dev))
	(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
	continue;		continue;

	if (dev->irq)		if (dev->irq)
	@@ -120,8 +128,7 @@ sio_collect_irq_levels(void)
	return level_bits;		return level_bits;
	}		}

	static void __init		static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
	sio_fixup_irq_levels(unsigned int level_bits)
	{		{
	unsigned int old_level_bits;		unsigned int old_level_bits;

	@@ -139,12 +146,21 @@ sio_fixup_irq_levels(unsigned int level_bits)
	*/		*/
	old_level_bits = inb(0x4d0) \| (inb(0x4d1) << 8);		old_level_bits = inb(0x4d0) \| (inb(0x4d1) << 8);

	level_bits \|= (old_level_bits & 0x71ff);		if (reset)
			old_level_bits &= 0x71ff;

			level_bits \|= old_level_bits;

	outb((level_bits >> 0) & 0xff, 0x4d0);		outb((level_bits >> 0) & 0xff, 0x4d0);
	outb((level_bits >> 8) & 0xff, 0x4d1);		outb((level_bits >> 8) & 0xff, 0x4d1);
	}		}

			static inline void
			sio_fixup_irq_levels(unsigned int level_bits)
			{
			__sio_fixup_irq_levels(level_bits, true);
			}

	static inline int		static inline int
	noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)		noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	{		{
	@@ -181,7 +197,14 @@ noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;		const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
	int irq = COMMON_TABLE_LOOKUP, tmp;		int irq = COMMON_TABLE_LOOKUP, tmp;
	tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);		tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
	return irq >= 0 ? tmp : -1;
			irq = irq >= 0 ? tmp : -1;

			/* Fixup IRQ level if an actual IRQ mapping is detected */
			if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
			__sio_fixup_irq_levels(1 << irq, false);

			return irq;
	}		}

	static inline int		static inline int

arch/arm/boot/dts/kirkwood-openblocks_a7.dts

+8 −2

Original line number	Original line	Diff line number	Diff line
	@@ -53,7 +53,8 @@
	};		};

	pinctrl: pin-controller@10000 {		pinctrl: pin-controller@10000 {
	pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;		pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
			&pmx_gpio_header_gpo>;
	pinctrl-names = "default";		pinctrl-names = "default";

	pmx_uart0: pmx-uart0 {		pmx_uart0: pmx-uart0 {
	@@ -85,11 +86,16 @@
	* ground.		* ground.
	*/		*/
	pmx_gpio_header: pmx-gpio-header {		pmx_gpio_header: pmx-gpio-header {
	marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",		marvell,pins = "mpp17", "mpp29", "mpp28",
	"mpp35", "mpp34", "mpp40";		"mpp35", "mpp34", "mpp40";
	marvell,function = "gpio";		marvell,function = "gpio";
	};		};

			pmx_gpio_header_gpo: pxm-gpio-header-gpo {
			marvell,pins = "mpp7";
			marvell,function = "gpo";
			};

	pmx_gpio_init: pmx-init {		pmx_gpio_init: pmx-init {
	marvell,pins = "mpp38";		marvell,pins = "mpp38";
	marvell,function = "gpio";		marvell,function = "gpio";

arch/arm/configs/sunxi_defconfig

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -10,6 +10,7 @@ CONFIG_SMP=y
	CONFIG_NR_CPUS=8		CONFIG_NR_CPUS=8
	CONFIG_AEABI=y		CONFIG_AEABI=y
	CONFIG_HIGHMEM=y		CONFIG_HIGHMEM=y
			CONFIG_CMA=y
	CONFIG_ARM_APPENDED_DTB=y		CONFIG_ARM_APPENDED_DTB=y
	CONFIG_ARM_ATAG_DTB_COMPAT=y		CONFIG_ARM_ATAG_DTB_COMPAT=y
	CONFIG_CPU_FREQ=y		CONFIG_CPU_FREQ=y
	@@ -33,6 +34,7 @@ CONFIG_CAN_SUN4I=y
	# CONFIG_WIRELESS is not set		# CONFIG_WIRELESS is not set
	CONFIG_DEVTMPFS=y		CONFIG_DEVTMPFS=y
	CONFIG_DEVTMPFS_MOUNT=y		CONFIG_DEVTMPFS_MOUNT=y
			CONFIG_DMA_CMA=y
	CONFIG_BLK_DEV_SD=y		CONFIG_BLK_DEV_SD=y
	CONFIG_ATA=y		CONFIG_ATA=y
	CONFIG_AHCI_SUNXI=y		CONFIG_AHCI_SUNXI=y