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Commit e6512624 authored by Len Brown's avatar Len Brown
Browse files

tools/power turbostat: further decode MSR_IA32_MISC_ENABLE 



Decode MISC_ENABLE.NO_TURBO,
also use the #defines in msr-index.h for decoding this register

cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)

Although it is not architectural, decode also
MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).
documented to be present on: Core, P4, Intel-Xeon
reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 710f273b

tools/power/x86/turbostat/turbostat.c

+6 −4
Original line number Original line Diff line number Diff line
@@ -3509,11 +3509,13 @@ void decode_misc_enable_msr(void) 
	unsigned long long msr;

	unsigned long long msr;





	if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))

	if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))

		fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",

		fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",

			base_cpu, msr,

			base_cpu, msr,

			msr & (1 << 3) ? "TCC" : "",

			msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",

			msr & (1 << 16) ? "EIST" : "",

			msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",

			msr & (1 << 18) ? "MONITOR" : "");

			msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "",

			msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",

			msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");

}

}





/*

/*