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Commit e60f8db5 authored by Alex Xie's avatar Alex Xie Committed by Alex Deucher
Browse files

drm/amdgpu: Add GMC 9.0 support (v2) 



On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

v2: drop sdma from Makefile, fix duplicate return statement.

Signed-off-by: default avatarAlex Xie <AlexBin.Xie@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1d83da9

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -39,7 +39,8 @@ amdgpu-y += \ 
# add GMC block

amdgpu-y += \

	gmc_v7_0.o \

	gmc_v8_0.o

	gmc_v8_0.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o



# add IH block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+30 −0
Original line number Diff line number Diff line
@@ -121,6 +121,11 @@ extern int amdgpu_param_buf_per_se; 
/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		2



/* max number of VMHUB */

#define AMDGPU_MAX_VMHUBS			2

#define AMDGPU_MMHUB				0

#define AMDGPU_GFXHUB				1



/* hardcode that limit for now */

#define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
@@ -308,6 +313,12 @@ struct amdgpu_gart_funcs { 
				     uint32_t flags);

};



/* provided by the mc block */

struct amdgpu_mc_funcs {

	/* adjust mc addr in fb for APU case */

	u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);

};



/* provided by the ih block */

struct amdgpu_ih_funcs {

	/* ring read/write ptr handling, called from interrupt context */
@@ -556,6 +567,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 
		     dma_addr_t *dma_addr, uint64_t flags);

int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);



/*

 * VMHUB structures, functions & helpers

 */

struct amdgpu_vmhub {

	uint32_t	ctx0_ptb_addr_lo32;

	uint32_t	ctx0_ptb_addr_hi32;

	uint32_t	vm_inv_eng0_req;

	uint32_t	vm_inv_eng0_ack;

	uint32_t	vm_context0_cntl;

	uint32_t	vm_l2_pro_fault_status;

	uint32_t	vm_l2_pro_fault_cntl;

	uint32_t	(*get_invalidate_req)(unsigned int vm_id);

	uint32_t	(*get_vm_protection_bits)(void);

};



/*

 * GPU MC structures, functions & helpers

 */
@@ -589,6 +615,9 @@ struct amdgpu_mc { 
	u64					shared_aperture_end;

	u64					private_aperture_start;

	u64					private_aperture_end;

	/* protects concurrent invalidation */

	spinlock_t		invalidate_lock;

	const struct amdgpu_mc_funcs *mc_funcs;

};



/*
@@ -1473,6 +1502,7 @@ struct amdgpu_device { 
	struct amdgpu_gart		gart;

	struct amdgpu_dummy_page	dummy_page;

	struct amdgpu_vm_manager	vm_manager;

	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];



	/* memory management */

	struct amdgpu_mman		mman;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+22 −6
Original line number Diff line number Diff line
@@ -447,6 +447,16 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) 
	return false;

}



static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)

{

	u64 addr = mc_addr;



	if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)

		addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);



	return addr;

}



/**

 * amdgpu_vm_flush - hardware flush the vm

 *
@@ -477,9 +487,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) 
	if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||

	    amdgpu_vm_is_gpu_reset(adev, id))) {

		struct dma_fence *fence;

		u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);



		trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id);

		amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);

		trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);

		amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);



		r = amdgpu_fence_emit(ring, &fence);

		if (r)
@@ -715,15 +726,18 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 
		    (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {



			if (count) {

				uint64_t pt_addr =

					amdgpu_vm_adjust_mc_addr(adev, last_pt);



				if (shadow)

					amdgpu_vm_do_set_ptes(&params,

							      last_shadow,

							      last_pt, count,

							      pt_addr, count,

							      incr,

							      AMDGPU_PTE_VALID);



				amdgpu_vm_do_set_ptes(&params, last_pde,

						      last_pt, count, incr,

						      pt_addr, count, incr,

						      AMDGPU_PTE_VALID);

			}
@@ -737,11 +751,13 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 
	}



	if (count) {

		uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);



		if (vm->page_directory->shadow)

			amdgpu_vm_do_set_ptes(&params, last_shadow, last_pt,

			amdgpu_vm_do_set_ptes(&params, last_shadow, pt_addr,

					      count, incr, AMDGPU_PTE_VALID);



		amdgpu_vm_do_set_ptes(&params, last_pde, last_pt,

		amdgpu_vm_do_set_ptes(&params, last_pde, pt_addr,

				      count, incr, AMDGPU_PTE_VALID);

	}

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

0 → 100644
+447 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu.h"

#include "gfxhub_v1_0.h"



#include "vega10/soc15ip.h"

#include "vega10/GC/gc_9_0_offset.h"

#include "vega10/GC/gc_9_0_sh_mask.h"

#include "vega10/GC/gc_9_0_default.h"

#include "vega10/vega10_enum.h"



#include "soc15_common.h"



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;

	u64 value;

	u32 i;



	/* Program MC. */

	/* Update configuration */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),

		adev->mc.vram_start >> 18);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),

		adev->mc.vram_end >> 18);



	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start

		+ adev->vm_manager.vram_base_offset;

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),

				(u32)(value >> 12));

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),

				(u32)(value >> 44));



	/* Disable AGP. */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);



	/* GART Enable. */



	/* Setup TLB control */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				SYSTEM_ACCESS_MODE,

				3);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				ENABLE_ADVANCED_DRIVER_MODEL,

				1);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				SYSTEM_APERTURE_UNMAPPED_ACCESS,

				0);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				ECO_BITS,

				0);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				MTYPE,

				MTYPE_UC);/* XXX for emulation. */

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				ATC_EN,

				1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				ENABLE_L2_FRAGMENT_PROCESSING,

				0);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				L2_PDE0_CACHE_TAG_GENERATION_MODE,

				0);/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				CONTEXT1_IDENTITY_ACCESS_MODE,

				1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				IDENTITY_MODE_FRAGMENT_SIZE,

				0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PDE_REQUEST_PHYSICAL,

			    0);

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PTE_REQUEST_PHYSICAL,

			    0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);



	/* setup context0 */

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

		(u32)(adev->mc.gtt_start >> 12));

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

		(u32)(adev->mc.gtt_start >> 44));



	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

		(u32)(adev->mc.gtt_end >> 12));

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

		(u32)(adev->mc.gtt_end >> 44));



	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));

	value = adev->gart.table_addr - adev->mc.vram_start

		+ adev->vm_manager.vram_base_offset;

	value &= 0x0000FFFFFFFFF000ULL;

	value |= 0x1; /*valid bit*/



	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),

		(u32)value);

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),

		(u32)(value >> 32));



	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),

		(u32)(adev->dummy_page.addr >> 12));

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),

		(u32)(adev->dummy_page.addr >> 44));



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,

			    1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);



	/* Disable identity aperture.*/

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);



	for (i = 0; i <= 14; i++) {

		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				PAGE_TABLE_BLOCK_SIZE,

				    amdgpu_vm_block_size - 9);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,

				adev->vm_manager.max_pfn - 1);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);

	}





	return 0;

}



void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)

{

	u32 tmp;

	u32 i;



	/* Disable all tables */

	for (i = 0; i < 16; i++)

		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);



	/* Setup TLB control */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				ENABLE_ADVANCED_DRIVER_MODEL,

				0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);

}



/**

 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling

 *

 * @adev: amdgpu_device pointer

 * @value: true redirects VM faults to the default page

 */

void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,

					  bool value)

{

	u32 tmp;

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp,

			VM_L2_PROTECTION_FAULT_CNTL,

			TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,

			value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);

}



static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)

{

	u32 req = 0;



	/* invalidate using legacy mode on vm_id*/

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

			    PER_VMID_INVALIDATE_REQ, 1 << vm_id);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);



	return req;

}



static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)

{

	return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

		    VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);

}



static int gfxhub_v1_0_early_init(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_late_init(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_sw_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];



	hub->ctx0_ptb_addr_lo32 =

		SOC15_REG_OFFSET(GC, 0,

				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);

	hub->ctx0_ptb_addr_hi32 =

		SOC15_REG_OFFSET(GC, 0,

				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);

	hub->vm_inv_eng0_req =

		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);

	hub->vm_inv_eng0_ack =

		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);

	hub->vm_context0_cntl =

		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);

	hub->vm_l2_pro_fault_status =

		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);

	hub->vm_l2_pro_fault_cntl =

		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);



	hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;

	hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;



	return 0;

}



static int gfxhub_v1_0_sw_fini(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_hw_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	unsigned i;



	for (i = 0 ; i < 18; ++i) {

		WREG32(SOC15_REG_OFFSET(GC, 0,

					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +

		       2 * i, 0xffffffff);

		WREG32(SOC15_REG_OFFSET(GC, 0,

					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +

		       2 * i, 0x1f);

	}



	return 0;

}



static int gfxhub_v1_0_hw_fini(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_suspend(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_resume(void *handle)

{

	return 0;

}



static bool gfxhub_v1_0_is_idle(void *handle)

{

	return true;

}



static int gfxhub_v1_0_wait_for_idle(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_soft_reset(void *handle)

{

	return 0;

}



static int gfxhub_v1_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{

	return 0;

}



static int gfxhub_v1_0_set_powergating_state(void *handle,

					  enum amd_powergating_state state)

{

	return 0;

}



const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {

	.name = "gfxhub_v1_0",

	.early_init = gfxhub_v1_0_early_init,

	.late_init = gfxhub_v1_0_late_init,

	.sw_init = gfxhub_v1_0_sw_init,

	.sw_fini = gfxhub_v1_0_sw_fini,

	.hw_init = gfxhub_v1_0_hw_init,

	.hw_fini = gfxhub_v1_0_hw_fini,

	.suspend = gfxhub_v1_0_suspend,

	.resume = gfxhub_v1_0_resume,

	.is_idle = gfxhub_v1_0_is_idle,

	.wait_for_idle = gfxhub_v1_0_wait_for_idle,

	.soft_reset = gfxhub_v1_0_soft_reset,

	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,

	.set_powergating_state = gfxhub_v1_0_set_powergating_state,

};



const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =

{

	.type = AMD_IP_BLOCK_TYPE_GFXHUB,

	.major = 1,

	.minor = 0,

	.rev = 0,

	.funcs = &gfxhub_v1_0_ip_funcs,

};

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h

0 → 100644
+35 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __GFXHUB_V1_0_H__

#define __GFXHUB_V1_0_H__



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);

void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);

void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,

					  bool value);



extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;

extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;



#endif