Merge "ARM: dts: msm: Add USB2 for sdmshrike" (e6041a09) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdmshrike-mtp.dtsi

+9 −0

Original line number	Diff line number	Diff line
		@@ -145,3 +145,12 @@

		status = "ok";
		};

		&usb2_phy1 {
		status = "ok";
		};

		&usb1 {
		qcom,default-mode-host;
		status ="ok";
		};

arch/arm64/boot/dts/qcom/sdmshrike-usb.dtsi

+104 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -136,4 +136,107 @@
		usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
		};

		/* Secondary USB port related controller */
		usb1: ssusb@a800000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x0a800000 0x100000>;
		reg-names = "core_base";

		iommus = <&apps_smmu 0x160 0x0>;
		qcom,smmu-s1-bypass;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>;
		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
		"ss_phy_irq", "dm_hs_phy_irq";
		qcom,use-pdc-interrupts;

		USB3_GDSC-supply = <&usb30_sec_gdsc>;
		clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>,
		<&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
		<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
		<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
		<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
		"utmi_clk", "sleep_clk", "xo";

		resets = <&clock_gcc GCC_USB30_SEC_BCR>;
		reset-names = "core_reset";

		qcom,core-clk-rate = <200000000>;
		qcom,core-clk-rate-hs = <66666667>;
		qcom,num-gsi-evt-buffs = <0x3>;
		qcom,gsi-reg-offset =
		<0x0fc /* GSI_GENERAL_CFG */
		0x110 /* GSI_DBL_ADDR_L */
		0x120 /* GSI_DBL_ADDR_H */
		0x130 /* GSI_RING_BASE_ADDR_L */
		0x144 /* GSI_RING_BASE_ADDR_H */
		0x1a4>; /* GSI_IF_STS */
		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
		qcom,charging-disabled;

		qcom,msm-bus,name = "usb1";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <3>;
		qcom,msm-bus,vectors-KBps =
		/* suspend vote */
		<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_EBI_CH0 0 0>,
		<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 0>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 0>,

		/* nominal vote */
		<MSM_BUS_MASTER_USB3_1
		MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
		<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>,

		/* svs vote */
		<MSM_BUS_MASTER_USB3_1
		MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
		<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>;

		status = "disabled";

		dwc3@a800000 {
		compatible = "snps,dwc3";
		reg = <0x0a800000 0xcd00>;
		interrupts = <0 138 0>;
		usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
		linux,sysdev_is_parent;
		snps,disable-clk-gating;
		snps,has-lpm-erratum;
		snps,hird-threshold = /bits/ 8 <0x10>;
		snps,usb3_lpm_capable;
		usb-core-id = <1>;
		tx-fifo-resize;
		maximum-speed = "high-speed";
		dr_mode = "otg";
		};
		};

		/* Secondary USB port related High Speed PHY */
		usb2_phy1: hsphy@88e3000 {
		compatible = "qcom,usb-hsphy-snps-femto";
		reg = <0x88e3000 0x110>;
		reg-names = "hsusb_phy_base";

		vdd-supply = <&pm8150_2_l5>;
		vdda18-supply = <&pm8150_1_l12>;
		vdda33-supply = <&pm8150_2_l16>;
		qcom,vdd-voltage-level = <0 880000 880000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "ref_clk_src";

		resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>;
		reset-names = "phy_reset";

		status = "disabled";
		};
		};