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Commit e52f649e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.1' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

radeon minor fixes, and pci id addition.
* 'drm-fixes-4.1' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: don't do mst probing if MST isn't enabled.
  drm/radeon: add new bonaire pci id
  drm/radeon: fix VM_CONTEXT*_PAGE_TABLE_END_ADDR handling
parents 030bbdbf bed447e7

drivers/gpu/drm/radeon/cik.c

+2 −2
Original line number Diff line number Diff line
@@ -5822,7 +5822,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	       L2_CACHE_BIGK_FRAGMENT_SIZE(4));

	/* setup context0 */

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

			(u32)(rdev->dummy_page.addr >> 12));
@@ -5837,7 +5837,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	/* restore context1-15 */

	/* set vm size, must be a multiple of 4 */

	WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);

	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);

	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);

	for (i = 1; i < 16; i++) {

		if (i < 8)

			WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

drivers/gpu/drm/radeon/evergreen.c

+1 −1
Original line number Diff line number Diff line
@@ -2485,7 +2485,7 @@ static int evergreen_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

drivers/gpu/drm/radeon/ni.c

+3 −2
Original line number Diff line number Diff line
@@ -1282,7 +1282,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) 
	       L2_CACHE_BIGK_FRAGMENT_SIZE(6));

	/* setup context0 */

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

			(u32)(rdev->dummy_page.addr >> 12));
@@ -1301,7 +1301,8 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) 
	 */

	for (i = 1; i < 8; i++) {

		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);

		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);

		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),

			rdev->vm_manager.max_pfn - 1);

		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

		       rdev->vm_manager.saved_table_addr[i]);

	}

drivers/gpu/drm/radeon/r600.c

+1 −1
Original line number Diff line number Diff line
@@ -1112,7 +1112,7 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

drivers/gpu/drm/radeon/radeon_dp_mst.c

+3 −0
Original line number Diff line number Diff line
@@ -666,6 +666,9 @@ radeon_dp_mst_probe(struct radeon_connector *radeon_connector) 
	int ret;

	u8 msg[1];



	if (!radeon_mst)

		return 0;



	if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)

		return 0;