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Commit e4f30545 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull second set of arm64 updates from Catalin Marinas:
 "A second pull request for this merging window, mainly with fixes and
  docs clarification:

   - Documentation clarification on CPU topology and booting
     requirements
   - Additional cache flushing during boot (needed in the presence of
     external caches or under virtualisation)
   - DMA range invalidation fix for non cache line aligned buffers
   - Build failure fix with !COMPAT
   - Kconfig update for STRICT_DEVMEM"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Fix DMA range invalidation for cache line unaligned buffers
  arm64: Add missing Kconfig for CONFIG_STRICT_DEVMEM
  arm64: fix !CONFIG_COMPAT build failures
  Revert "arm64: virt: ensure visibility of __boot_cpu_mode"
  arm64: Relax the kernel cache requirements for boot
  arm64: Update the TCR_EL1 translation granule definitions for 16K pages
  ARM: topology: Make it clear that all CPUs need to be described
parents d586c86d ebf81a93

Documentation/arm64/booting.txt

+8 −2
Original line number Diff line number Diff line
@@ -111,8 +111,14 @@ Before jumping into the kernel, the following conditions must be met: 
- Caches, MMUs

  The MMU must be off.

  Instruction cache may be on or off.

  Data cache must be off and invalidated.

  External caches (if present) must be configured and disabled.

  The address range corresponding to the loaded kernel image must be

  cleaned to the PoC. In the presence of a system cache or other

  coherent masters with caches enabled, this will typically require

  cache maintenance by VA rather than set/way operations.

  System caches which respect the architected cache maintenance by VA

  operations must be configured and may be enabled.

  System caches which do not respect architected cache maintenance by VA

  operations (not recommended) must be configured and disabled.



- Architected timers

  CNTFRQ must be programmed with the timer frequency and CNTVOFF must

Documentation/devicetree/bindings/arm/topology.txt

+4 −3
Original line number Diff line number Diff line
@@ -75,9 +75,10 @@ The cpu-map node can only contain three types of child nodes: 


whose bindings are described in paragraph 3.



The nodes describing the CPU topology (cluster/core/thread) can only be

defined within the cpu-map node.

Any other configuration is consider invalid and therefore must be ignored.

The nodes describing the CPU topology (cluster/core/thread) can only

be defined within the cpu-map node and every core/thread in the system

must be defined within the topology.  Any other configuration is

invalid and therefore must be ignored.



===========================================

2.1 - cpu-map child nodes naming convention

arch/arm64/Kconfig.debug

+14 −0
Original line number Diff line number Diff line
@@ -6,6 +6,20 @@ config FRAME_POINTER 
	bool

	default y



config STRICT_DEVMEM

	bool "Filter access to /dev/mem"

	depends on MMU

	help

	  If this option is disabled, you allow userspace (root) access to all

	  of memory, including kernel and userspace memory. Accidental

	  access to this is obviously disastrous, but specific access can

	  be used by people debugging the kernel.



	  If this option is switched on, the /dev/mem file only allows

	  userspace access to memory mapped peripherals.



	  If in doubt, say Y.



config EARLY_PRINTK

	bool "Early printk support"

	default y

arch/arm64/include/asm/pgtable-hwdef.h

+5 −1
Original line number Diff line number Diff line
@@ -120,8 +120,12 @@ 
#define TCR_ORGN_WBnWA		((UL(3) << 10) | (UL(3) << 26))

#define TCR_ORGN_MASK		((UL(3) << 10) | (UL(3) << 26))

#define TCR_SHARED		((UL(3) << 12) | (UL(3) << 28))

#define TCR_TG0_4K		(UL(0) << 14)

#define TCR_TG0_64K		(UL(1) << 14)

#define TCR_TG1_64K		(UL(1) << 30)

#define TCR_TG0_16K		(UL(2) << 14)

#define TCR_TG1_16K		(UL(1) << 30)

#define TCR_TG1_4K		(UL(2) << 30)

#define TCR_TG1_64K		(UL(3) << 30)

#define TCR_ASID16		(UL(1) << 36)

#define TCR_TBI0		(UL(1) << 37)

arch/arm64/include/asm/virt.h

+0 −13
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#define BOOT_CPU_MODE_EL2	(0xe12)



#ifndef __ASSEMBLY__

#include <asm/cacheflush.h>



/*

 * __boot_cpu_mode records what mode CPUs were booted in.
@@ -38,20 +37,9 @@ extern u32 __boot_cpu_mode[2]; 
void __hyp_set_vectors(phys_addr_t phys_vector_base);

phys_addr_t __hyp_get_vectors(void);



static inline void sync_boot_mode(void)

{

	/*

	 * As secondaries write to __boot_cpu_mode with caches disabled, we

	 * must flush the corresponding cache entries to ensure the visibility

	 * of their writes.

	 */

	__flush_dcache_area(__boot_cpu_mode, sizeof(__boot_cpu_mode));

}



/* Reports the availability of HYP mode */

static inline bool is_hyp_mode_available(void)

{

	sync_boot_mode();

	return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 &&

		__boot_cpu_mode[1] == BOOT_CPU_MODE_EL2);

}
@@ -59,7 +47,6 @@ static inline bool is_hyp_mode_available(void) 
/* Check if the bootloader has booted CPUs in different modes */

static inline bool is_hyp_mode_mismatched(void)

{

	sync_boot_mode();

	return __boot_cpu_mode[0] != __boot_cpu_mode[1];

}