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Commit e4225ae8 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by Boris Brezillon
Browse files

mtd: mtd: drop NAND_ECC_SOFT_BCH enum value 



This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent ae211bcf

drivers/mtd/nand/fsmc_nand.c

+1 −2
Original line number Diff line number Diff line
@@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) 
			break;



		case NAND_ECC_SOFT:

		case NAND_ECC_SOFT_BCH:

			if (nand->ecc.algo == NAND_ECC_BCH) {

				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");

				break;
@@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) 
		 * Don't set layout for BCH4 SW ECC. This will be

		 * generated later in nand_bch_init() later.

		 */

		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {

		if (nand->ecc.mode == NAND_ECC_HW) {

			switch (mtd->oobsize) {

			case 16:

			case 64:

drivers/mtd/nand/jz4780_nand.c

+0 −1
Original line number Diff line number Diff line
@@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de 
		chip->ecc.correct = jz4780_nand_ecc_correct;

		/* fall through */

	case NAND_ECC_SOFT:

	case NAND_ECC_SOFT_BCH:

		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",

			(nfc->bch) ? "hardware BCH" : "software ECC",

			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);

drivers/mtd/nand/mxc_nand.c

+0 −1
Original line number Diff line number Diff line
@@ -1625,7 +1625,6 @@ static int mxcnd_probe(struct platform_device *pdev) 
		break;



	case NAND_ECC_SOFT:

	case NAND_ECC_SOFT_BCH:

		break;



	default:

drivers/mtd/nand/nand_base.c

+3 −8
Original line number Diff line number Diff line
@@ -4183,8 +4183,7 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd) 
	struct nand_chip *chip = mtd_to_nand(mtd);

	struct nand_ecc_ctrl *ecc = &chip->ecc;



	if (WARN_ON(ecc->mode != NAND_ECC_SOFT &&

		    ecc->mode != NAND_ECC_SOFT_BCH))

	if (WARN_ON(ecc->mode != NAND_ECC_SOFT))

		return -EINVAL;



	switch (ecc->algo) {
@@ -4331,8 +4330,7 @@ int nand_scan_tail(struct mtd_info *mtd) 
	 * If no default placement scheme is given, select an appropriate one.

	 */

	if (!mtd->ooblayout &&

	    !((ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&

	       ecc->algo == NAND_ECC_BCH)) {

	    !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {

		switch (mtd->oobsize) {

		case 8:

		case 16:
@@ -4426,7 +4424,6 @@ int nand_scan_tail(struct mtd_info *mtd) 
		ecc->algo = NAND_ECC_HAMMING;



	case NAND_ECC_SOFT:

	case NAND_ECC_SOFT_BCH:

		ret = nand_set_ecc_soft_ops(mtd);

		if (ret) {

			ret = -EINVAL;
@@ -4514,7 +4511,6 @@ int nand_scan_tail(struct mtd_info *mtd) 
	/* Large page NAND with SOFT_ECC should support subpage reads */

	switch (ecc->mode) {

	case NAND_ECC_SOFT:

	case NAND_ECC_SOFT_BCH:

		if (chip->page_shift > 9)

			chip->options |= NAND_SUBPAGE_READ;

		break;
@@ -4614,8 +4610,7 @@ void nand_release(struct mtd_info *mtd) 
{

	struct nand_chip *chip = mtd_to_nand(mtd);



	if ((chip->ecc.mode == NAND_ECC_SOFT ||

	     chip->ecc.mode == NAND_ECC_SOFT_BCH) &&

	if (chip->ecc.mode == NAND_ECC_SOFT &&

	    chip->ecc.algo == NAND_ECC_BCH)

		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);

drivers/mtd/nand/nandsim.c

+1 −1
Original line number Diff line number Diff line
@@ -2339,7 +2339,7 @@ static int __init ns_init_module(void) 
			retval = -EINVAL;

			goto error;

		}

		chip->ecc.mode = NAND_ECC_SOFT_BCH;

		chip->ecc.mode = NAND_ECC_SOFT;

		chip->ecc.algo = NAND_ECC_BCH;

		chip->ecc.size = 512;

		chip->ecc.strength = bch;