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Commit e399b1a4 authored by Russell King's avatar Russell King
Browse files

ARM: v6k: introduce CPU_V6K option



Introduce a CPU_V6K configuration option for platforms to select if they
have a V6K CPU core.  This allows us to identify whether we need to
support ARMv6 CPUs without the V6K SMP extensions at build time.

Currently CPU_V6K is just an alias for CPU_V6, and all places which
reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K).

Select CPU_V6K from platforms which are known to be V6K-only.

Acked-by: default avatarTony Lindgren <tony@atomide.com>
Tested-by: default avatarSourav Poddar <sourav.poddar@ti.com>
Tested-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 000d9c78
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+5 −5
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ config ARM
	select HAVE_PERF_EVENTS
	select PERF_USE_VMALLOC
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
	select HAVE_C_RECORDMCOUNT
	select HAVE_GENERIC_HARDIRQS
	select HAVE_SPARSE_IRQ
@@ -1048,7 +1048,7 @@ config XSCALE_PMU
	default y

config CPU_HAS_PMU
	depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
		   (!ARCH_OMAP3 || OMAP3_EMU)
	default y
	bool
@@ -1064,7 +1064,7 @@ endif

config ARM_ERRATA_411920
	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
	depends on CPU_V6
	depends on CPU_V6 || CPU_V6K
	help
	  Invalidation of the Instruction Cache operation can
	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1361,7 +1361,7 @@ config HZ

config THUMB2_KERNEL
	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
	depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
	select AEABI
	select ARM_ASM_UNIFIED
	help
@@ -1852,7 +1852,7 @@ config FPE_FASTFPE

config VFP
	bool "VFP-format floating point maths"
	depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
	help
	  Say Y to include VFP support code in the kernel. This is needed
	  if your hardware includes a VFP unit.
+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110)
tune-$(CONFIG_CPU_XSC3)		:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
tune-$(CONFIG_CPU_FEROCEON)	:=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
tune-$(CONFIG_CPU_V6)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
tune-$(CONFIG_CPU_V6K)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

ifeq ($(CONFIG_AEABI),y)
CFLAGS_ABI	:=-mabi=aapcs-linux -mno-thumb-interwork
+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@

#if defined(CONFIG_DEBUG_ICEDCC)

#ifdef CONFIG_CPU_V6
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
		.macro	loadsp, rb, tmp
		.endm
		.macro	writeb, ch, rb
+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ extern void error(char *x);

#ifdef CONFIG_DEBUG_ICEDCC

#ifdef CONFIG_CPU_V6
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)

static void icedcc_putc(int ch)
{
+3 −2
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@
# define MULTI_CACHE 1
#endif

#if defined(CONFIG_CPU_V6)
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
//# ifdef _CACHE
#  define MULTI_CACHE 1
//# else
@@ -316,7 +316,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
 * will fall through to use __flush_icache_all_generic.
 */
#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||		\
#if (defined(CONFIG_CPU_V7) && \
     (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
	defined(CONFIG_SMP_ON_UP)
#define __flush_icache_preferred	__cpuc_flush_icache_all
#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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