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Commit e3812ce4 authored by Florian Tobias Schandinat's avatar Florian Tobias Schandinat
Browse files

viafb: reset correct PLL 



Looks like we did reset the PLL of the (whatever) engine instead of
the PLL of the secondary display (IGA2, LCDCK). This patch fixes it.

Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Joseph Chan <JosephChan@via.com.tw>
parent b4aaa78f

drivers/video/via/hw.c

+2 −2
Original line number Diff line number Diff line
@@ -1688,8 +1688,8 @@ void viafb_set_vclock(u32 clk, int set_iga) 
	}



	if (set_iga == IGA2) {

		viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);

		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);

		viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);

		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);

	}



	/* Fire! */