Merge branch 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux into drm-fixes (e2cdcafa) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/radeon/radeon_fence.c

+45 −23

Original line number	Original line	Diff line number	Diff line
	@@ -1030,37 +1030,59 @@ static inline bool radeon_test_signaled(struct radeon_fence *fence)
	return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);		return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
	}		}

			struct radeon_wait_cb {
			struct fence_cb base;
			struct task_struct *task;
			};

			static void
			radeon_fence_wait_cb(struct fence fence, struct fence_cb cb)
			{
			struct radeon_wait_cb *wait =
			container_of(cb, struct radeon_wait_cb, base);

			wake_up_process(wait->task);
			}

	static signed long radeon_fence_default_wait(struct fence *f, bool intr,		static signed long radeon_fence_default_wait(struct fence *f, bool intr,
	signed long t)		signed long t)
	{		{
	struct radeon_fence *fence = to_radeon_fence(f);		struct radeon_fence *fence = to_radeon_fence(f);
	struct radeon_device *rdev = fence->rdev;		struct radeon_device *rdev = fence->rdev;
	bool signaled;		struct radeon_wait_cb cb;

	fence_enable_sw_signaling(&fence->base);		cb.task = current;

	/*		if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
	* This function has to return -EDEADLK, but cannot hold		return t;
	* exclusive_lock during the wait because some callers
	* may already hold it. This means checking needs_reset without
	* lock, and not fiddling with any gpu internals.
	*
	* The callback installed with fence_enable_sw_signaling will
	* run before our wait_event_*timeout call, so we will see
	* both the signaled fence and the changes to needs_reset.
	*/

			while (t > 0) {
	if (intr)		if (intr)
	t = wait_event_interruptible_timeout(rdev->fence_queue,		set_current_state(TASK_INTERRUPTIBLE);
	((signaled = radeon_test_signaled(fence)) \|\|
	rdev->needs_reset), t);
	else		else
	t = wait_event_timeout(rdev->fence_queue,		set_current_state(TASK_UNINTERRUPTIBLE);
	((signaled = radeon_test_signaled(fence)) \|\|
	rdev->needs_reset), t);		/*
			* radeon_test_signaled must be called after
			* set_current_state to prevent a race with wake_up_process
			*/
			if (radeon_test_signaled(fence))
			break;

			if (rdev->needs_reset) {
			t = -EDEADLK;
			break;
			}

			t = schedule_timeout(t);

			if (t > 0 && intr && signal_pending(current))
			t = -ERESTARTSYS;
			}

			__set_current_state(TASK_RUNNING);
			fence_remove_callback(f, &cb.base);

	if (t > 0 && !signaled)
	return -EDEADLK;
	return t;		return t;
	}		}

drivers/gpu/drm/radeon/si.c

+2 −4

Original line number	Original line	Diff line number	Diff line
	@@ -7130,8 +7130,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

	if (!vclk \|\| !dclk) {		if (!vclk \|\| !dclk) {
	/* keep the Bypass mode, put PLL to sleep */		/* keep the Bypass mode */
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
	return 0;		return 0;
	}		}

	@@ -7147,8 +7146,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	/* set VCO_MODE to 1 */		/* set VCO_MODE to 1 */
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

	/* toggle UPLL_SLEEP to 1 then back to 0 */		/* disable sleep mode */
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

	/* deassert UPLL_RESET */		/* deassert UPLL_RESET */