Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e210a961 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "mtd: msm_qpic_nand: Add new BAM Pipe configuration changes"

parents 62835b94 5db02d48

drivers/mtd/devices/msm_qpic_nand.c

+24 −2
Original line number Diff line number Diff line
@@ -3062,7 +3062,8 @@ static int msm_nand_init_endpoint(struct msm_nand_info *info, 
		goto free_endpoint;

	}



	if (pipe_index == SPS_DATA_PROD_PIPE_INDEX) {

	if (pipe_index == SPS_DATA_PROD_PIPE_INDEX ||

		pipe_index == SPS_DATA_PROD_STAT_PIPE_INDEX) {

		/* READ CASE: source - BAM; destination - system memory */

		sps_config->source = info->sps.bam_handle;

		sps_config->destination = SPS_DEV_HANDLE_MEM;
@@ -3081,7 +3082,8 @@ static int msm_nand_init_endpoint(struct msm_nand_info *info, 
				SPS_O_ACK_TRANSFERS;



	if (pipe_index == SPS_DATA_PROD_PIPE_INDEX ||

			pipe_index == SPS_DATA_CONS_PIPE_INDEX)

			pipe_index == SPS_DATA_CONS_PIPE_INDEX ||

			pipe_index == SPS_DATA_PROD_STAT_PIPE_INDEX)

		sps_config->lock_group = BAM_APPS_PIPE_LOCK_GRP0;

	else if (pipe_index == SPS_CMD_CONS_PIPE_INDEX)

		sps_config->lock_group = BAM_APPS_PIPE_LOCK_GRP1;
@@ -3219,6 +3221,9 @@ static void msm_nand_bam_free(struct msm_nand_info *nand_info) 
	msm_nand_deinit_endpoint(nand_info, &nand_info->sps.data_prod);

	msm_nand_deinit_endpoint(nand_info, &nand_info->sps.data_cons);

	msm_nand_deinit_endpoint(nand_info, &nand_info->sps.cmd_pipe);

	if (nand_info->nand_chip.qpic_version >= 2)

		msm_nand_deinit_endpoint(nand_info,

			&nand_info->sps.data_prod_stat);

}



/* This function enables DMA support for the NANDc in BAM mode. */
@@ -3376,6 +3381,7 @@ static int msm_nand_probe(struct platform_device *pdev) 
	u32 adjustment_offset;

	void __iomem *boot_cfg_base;

	u32 boot_dev;

	struct version qpic_version = {0};



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						"boot_cfg");
@@ -3512,6 +3518,22 @@ static int msm_nand_probe(struct platform_device *pdev) 
		pr_err("Failed to enable DMA in NANDc\n");

		goto free_bam;

	}

	err = msm_nand_version_check(info, &qpic_version);

	if (err) {

		pr_err("Failed to read the version information\n");

		goto free_bam;

	}

	info->nand_chip.qpic_version = qpic_version.qpic_major;

	if (info->nand_chip.qpic_version >= 2) {

		err = msm_nand_init_endpoint(info,

			&info->sps.data_prod_stat,

			SPS_DATA_PROD_STAT_PIPE_INDEX);

		if (err) {

			pr_err("Failed to configure read status pipe err=%d\n",

				err);

			goto free_bam;

		}

	}

	err = msm_nand_parse_smem_ptable(&nr_parts);

	if (err < 0) {

		pr_err("Failed to parse partition table in SMEM\n");

drivers/mtd/devices/msm_qpic_nand.h

+3 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
#define SPS_DATA_CONS_PIPE_INDEX 0

#define SPS_DATA_PROD_PIPE_INDEX 1

#define SPS_CMD_CONS_PIPE_INDEX 2

#define SPS_DATA_PROD_STAT_PIPE_INDEX 3



#define msm_virt_to_dma(chip, vaddr) \

	((chip)->dma_phys_addr + \
@@ -251,6 +252,7 @@ struct msm_nand_chip { 
	uint32_t ecc_buf_cfg;

	uint32_t ecc_bch_cfg;

	uint32_t ecc_cfg_raw;

	uint32_t qpic_version; /* To store the qpic controller version */

};



/* Structure that defines an SPS end point for a NANDc BAM pipe. */
@@ -271,6 +273,7 @@ struct msm_nand_sps_info { 
	struct msm_nand_sps_endpt data_prod;

	struct msm_nand_sps_endpt data_cons;

	struct msm_nand_sps_endpt cmd_pipe;

	struct msm_nand_sps_endpt data_prod_stat;

};



/*