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Commit e1c878d2 authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

clk: qcom: Add camera clock driver for SM6150 



Add support for camera clock controller found on SM6150
based devices. This would allow camera device drivers
to probe and control their clocks.

Change-Id: I9fdfd9b0f4411dc87e6dec1ca95ebb69ee621db0
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent cecc0b27

Documentation/devicetree/bindings/clock/qcom,camcc.txt

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding 


Required properties :

- compatible : must contain "qcom,camcc-sm8150", "qcom,camcc-sm8150-v2"

	       or "qcom,camcc-sdmshrike".

	       or "qcom,camcc-sdmshrike" or "qcom,camcc-sm6150".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -376,3 +376,12 @@ config MSM_DEBUGCC_SM6150 
	  Support for the debug clock controller on Qualcomm Technologies, Inc

	  SM6150 devices.

	  Say Y if you want to support the clock measurement functionality.



config MSM_CAMCC_SM6150

	tristate "SM6150 Cameira Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the camera clock controller on Qualcomm Technologies, Inc

	  SM6150 devices.

	  Say Y if you want to support camera devices and functionality such as

	  capturing pictures.

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o 
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o

obj-$(CONFIG_MDM_GCC_QCS405) += gcc-qcs405.o

obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o

obj-$(CONFIG_MSM_CAMCC_SM6150) += camcc-sm6150.o

obj-$(CONFIG_MSM_CAMCC_SM8150) += camcc-sm8150.o

obj-$(CONFIG_MSM_CAMCC_SDMSHRIKE) += camcc-sdmshrike.o

obj-$(CONFIG_MSM_CLK_AOP_QMP) += clk-aop-qmp.o

drivers/clk/qcom/camcc-sm6150.c

0 → 100644
+1783 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,camcc-sm6150.h

+72 −104
Original line number Diff line number Diff line
@@ -14,109 +14,77 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM6150_H



#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2

#define CAM_CC_BPS_CLK						3

#define CAM_CC_BPS_CLK_SRC					4

#define CAM_CC_CAMNOC_ATB_CLK					5

#define CAM_CC_CAMNOC_AXI_CLK					6

#define CAM_CC_CCI_CLK						7

#define CAM_CC_CCI_CLK_SRC					8

#define CAM_CC_CORE_AHB_CLK					9

#define CAM_CC_CPAS_AHB_CLK					10

#define CAM_CC_CPHY_RX_CLK_SRC					11

#define CAM_CC_CSI0PHYTIMER_CLK					12

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				13

#define CAM_CC_CSI1PHYTIMER_CLK					14

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				15

#define CAM_CC_CSI2PHYTIMER_CLK					16

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				17

#define CAM_CC_CSIPHY0_CLK					18

#define CAM_CC_CSIPHY1_CLK					19

#define CAM_CC_CSIPHY2_CLK					20

#define CAM_CC_DEBUG_CLK					21

#define CAM_CC_FAST_AHB_CLK_SRC					22

#define CAM_CC_ICP_APB_CLK					23

#define CAM_CC_ICP_ATB_CLK					24

#define CAM_CC_ICP_CLK						25

#define CAM_CC_ICP_CLK_SRC					26

#define CAM_CC_ICP_CTI_CLK					27

#define CAM_CC_ICP_TS_CLK					28

#define CAM_CC_IFE_0_AXI_CLK					29

#define CAM_CC_IFE_0_CLK					30

#define CAM_CC_IFE_0_CLK_SRC					31

#define CAM_CC_IFE_0_CPHY_RX_CLK				32

#define CAM_CC_IFE_0_CSID_CLK					33

#define CAM_CC_IFE_0_CSID_CLK_SRC				34

#define CAM_CC_IFE_0_DSP_CLK					35

#define CAM_CC_IFE_1_AXI_CLK					36

#define CAM_CC_IFE_1_CLK					37

#define CAM_CC_IFE_1_CLK_SRC					38

#define CAM_CC_IFE_1_CPHY_RX_CLK				39

#define CAM_CC_IFE_1_CSID_CLK					40

#define CAM_CC_IFE_1_CSID_CLK_SRC				41

#define CAM_CC_IFE_1_DSP_CLK					42

#define CAM_CC_IFE_LITE_CLK					43

#define CAM_CC_IFE_LITE_CLK_SRC					44

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				45

#define CAM_CC_IFE_LITE_CSID_CLK				46

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				47

#define CAM_CC_IPE_0_AHB_CLK					48

#define CAM_CC_IPE_0_AREG_CLK					49

#define CAM_CC_IPE_0_AXI_CLK					50

#define CAM_CC_IPE_0_CLK					51

#define CAM_CC_IPE_0_CLK_SRC					52

#define CAM_CC_JPEG_CLK						53

#define CAM_CC_JPEG_CLK_SRC					54

#define CAM_CC_LRME_CLK						55

#define CAM_CC_LRME_CLK_SRC					56

#define CAM_CC_MCLK0_CLK					57

#define CAM_CC_MCLK0_CLK_SRC					58

#define CAM_CC_MCLK1_CLK					59

#define CAM_CC_MCLK1_CLK_SRC					60

#define CAM_CC_MCLK2_CLK					61

#define CAM_CC_MCLK2_CLK_SRC					62

#define CAM_CC_MCLK3_CLK					63

#define CAM_CC_MCLK3_CLK_SRC					64

#define CAM_CC_PLL0						65

#define CAM_CC_PLL0_OUT_AUX					66

#define CAM_CC_PLL1						67

#define CAM_CC_PLL1_OUT_AUX					68

#define CAM_CC_PLL2						69

#define CAM_CC_PLL2_OUT_AUX2					70

#define CAM_CC_PLL3						71

#define CAM_CC_PLL3_OUT_MAIN					72

#define CAM_CC_PLL_TEST_CLK					73

#define CAM_CC_SLOW_AHB_CLK_SRC					74

#define CAM_CC_SOC_AHB_CLK					75

#define CAM_CC_SPDM_BPS_CLK					76

#define CAM_CC_SPDM_IFE_0_CLK					77

#define CAM_CC_SPDM_IFE_0_CSID_CLK				78

#define CAM_CC_SPDM_IPE_0_CLK					79

#define CAM_CC_SPDM_JPEG_CLK					80

#define CAM_CC_SYS_TMR_CLK					81



/* TODO: Add PLL Clock IDs */



#define CAM_CC_BPS_BCR						0

#define CAM_CC_CAMNOC_BCR					1

#define CAM_CC_CCI_BCR						2

#define CAM_CC_CPAS_BCR						3

#define CAM_CC_CSI0PHY_BCR					4

#define CAM_CC_CSI1PHY_BCR					5

#define CAM_CC_CSI2PHY_BCR					6

#define CAM_CC_ICP_BCR						7

#define CAM_CC_IFE_0_BCR					8

#define CAM_CC_IFE_1_BCR					9

#define CAM_CC_IFE_LITE_BCR					10

#define CAM_CC_IPE_0_BCR					11

#define CAM_CC_JPEG_BCR						12

#define CAM_CC_LRME_BCR						13

#define CAM_CC_MCLK0_BCR					14

#define CAM_CC_MCLK1_BCR					15

#define CAM_CC_MCLK2_BCR					16

#define CAM_CC_MCLK3_BCR					17

#define CAM_CC_TITAN_TOP_BCR					18

#define CAM_CC_PLL0_OUT_AUX					0

#define CAM_CC_PLL1_OUT_AUX					1

#define CAM_CC_PLL2_OUT_EARLY					2

#define CAM_CC_PLL2_OUT_AUX2					3

#define CAM_CC_PLL3_OUT_MAIN					4

#define CAM_CC_BPS_AHB_CLK					5

#define CAM_CC_BPS_AREG_CLK					6

#define CAM_CC_BPS_AXI_CLK					7

#define CAM_CC_BPS_CLK						8

#define CAM_CC_BPS_CLK_SRC					9

#define CAM_CC_CAMNOC_ATB_CLK					10

#define CAM_CC_CAMNOC_AXI_CLK					11

#define CAM_CC_CCI_CLK						12

#define CAM_CC_CCI_CLK_SRC					13

#define CAM_CC_CORE_AHB_CLK					14

#define CAM_CC_CPAS_AHB_CLK					15

#define CAM_CC_CPHY_RX_CLK_SRC					16

#define CAM_CC_CSI0PHYTIMER_CLK					17

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				18

#define CAM_CC_CSI1PHYTIMER_CLK					19

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				20

#define CAM_CC_CSI2PHYTIMER_CLK					21

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				22

#define CAM_CC_CSIPHY0_CLK					23

#define CAM_CC_CSIPHY1_CLK					24

#define CAM_CC_CSIPHY2_CLK					25

#define CAM_CC_FAST_AHB_CLK_SRC					26

#define CAM_CC_ICP_APB_CLK					27

#define CAM_CC_ICP_ATB_CLK					28

#define CAM_CC_ICP_CLK						29

#define CAM_CC_ICP_CLK_SRC					30

#define CAM_CC_ICP_CTI_CLK					31

#define CAM_CC_ICP_TS_CLK					32

#define CAM_CC_IFE_0_AXI_CLK					33

#define CAM_CC_IFE_0_CLK					34

#define CAM_CC_IFE_0_CLK_SRC					35

#define CAM_CC_IFE_0_CPHY_RX_CLK				36

#define CAM_CC_IFE_0_CSID_CLK					37

#define CAM_CC_IFE_0_CSID_CLK_SRC				38

#define CAM_CC_IFE_0_DSP_CLK					39

#define CAM_CC_IFE_1_AXI_CLK					40

#define CAM_CC_IFE_1_CLK					41

#define CAM_CC_IFE_1_CLK_SRC					42

#define CAM_CC_IFE_1_CPHY_RX_CLK				43

#define CAM_CC_IFE_1_CSID_CLK					44

#define CAM_CC_IFE_1_CSID_CLK_SRC				45

#define CAM_CC_IFE_1_DSP_CLK					46

#define CAM_CC_IFE_LITE_CLK					47

#define CAM_CC_IFE_LITE_CLK_SRC					48

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				49

#define CAM_CC_IFE_LITE_CSID_CLK				50

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				51

#define CAM_CC_IPE_0_AHB_CLK					52

#define CAM_CC_IPE_0_AREG_CLK					53

#define CAM_CC_IPE_0_AXI_CLK					54

#define CAM_CC_IPE_0_CLK					55

#define CAM_CC_IPE_0_CLK_SRC					56

#define CAM_CC_JPEG_CLK						57

#define CAM_CC_JPEG_CLK_SRC					58

#define CAM_CC_LRME_CLK						59

#define CAM_CC_LRME_CLK_SRC					60

#define CAM_CC_MCLK0_CLK					61

#define CAM_CC_MCLK0_CLK_SRC					62

#define CAM_CC_MCLK1_CLK					63

#define CAM_CC_MCLK1_CLK_SRC					64

#define CAM_CC_MCLK2_CLK					65

#define CAM_CC_MCLK2_CLK_SRC					66

#define CAM_CC_MCLK3_CLK					67

#define CAM_CC_MCLK3_CLK_SRC					68

#define CAM_CC_SLOW_AHB_CLK_SRC					69

#define CAM_CC_SOC_AHB_CLK					70

#define CAM_CC_SYS_TMR_CLK					71



#endif