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Commit e0661387 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "spi: spi-geni-qcom: Allow MISO<->MOSI connectivity for slave pins"

parents 4646efa1 005c3a05

Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ Optional properties: 
			transfers. FIFO mode does not work when FW of SE

			is configured in GSI mode.



- slv-cross-connected : Set this flag only when SPI-Slave MISO pin is connected

			to SPI-Master MOSI and vice-versa .



Other optional properties described in

Documentation/devicetree/bindings/spi/spi-bus.txt

drivers/spi/spi-geni-qcom.c

+11 −2
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ struct spi_geni_master { 
	int num_tx_eot;

	int num_rx_eot;

	int num_xfers;

	bool slave_cross_connected;

	void *ipc;

	bool shared_se;

	bool dis_autosuspend;
@@ -205,8 +206,14 @@ static void spi_slv_setup(struct spi_geni_master *mas) 
{

	geni_write_reg(SPI_SLAVE_EN, mas->base, SE_SPI_SLAVE_EN);



	geni_write_reg(1, mas->base, GENI_OUTPUT_CTRL);



	if (mas->slave_cross_connected) {

		geni_write_reg(GENI_IO_MUX_1_EN, mas->base, GENI_OUTPUT_CTRL);

		geni_write_reg(IO1_SEL_TX | IO2_DATA_IN_SEL_PAD2 |

						IO3_DATA_IN_SEL_PAD2,

						mas->base, GENI_CFG_REG80);

	} else {

		geni_write_reg(GENI_IO_MUX_0_EN, mas->base, GENI_OUTPUT_CTRL);

	}

	geni_write_reg(START_TRIGGER, mas->base, SE_GENI_CFG_SEQ_START);

	/* ensure data is written to hardware register */

	wmb();
@@ -1605,6 +1612,8 @@ static int spi_geni_probe(struct platform_device *pdev) 
		spi->slave_abort = spi_slv_abort;

	}



	geni_mas->slave_cross_connected =

		of_property_read_bool(pdev->dev.of_node, "slv-cross-connected");

	spi->mode_bits = (SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH);

	spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	spi->num_chipselect = SPI_NUM_CHIPSELECT;

include/linux/qcom-geni-se.h

+8 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ struct se_geni_rsc { 
#define SE_GENI_CLK_SEL			(0x7C)

#define SE_GENI_CFG_SEQ_START			(0x84)

#define SE_GENI_CFG_REG		(0x200)

#define GENI_CFG_REG80			(0x240)

#define SE_GENI_BYTE_GRAN		(0x254)

#define SE_GENI_DMA_MODE_EN		(0x258)

#define SE_GENI_TX_PACKING_CFG0		(0x260)
@@ -140,6 +141,13 @@ struct se_geni_rsc { 


/* GENI_OUTPUT_CTRL fields */

#define DEFAULT_IO_OUTPUT_CTRL_MSK	(GENMASK(6, 0))

#define GENI_IO_MUX_0_EN			BIT(1)

#define GENI_IO_MUX_1_EN			BIT(2)



/* GENI_CFG_REG80 fields */

#define IO1_SEL_TX			BIT(2)

#define IO2_DATA_IN_SEL_PAD2	(GENMASK(11, 10))

#define IO3_DATA_IN_SEL_PAD2	BIT(15)



/* GENI_FORCE_DEFAULT_REG fields */

#define FORCE_DEFAULT	(BIT(0))