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Commit e0563e04 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'perf/urgent' into perf/core, to pick up fixes 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents b00233b5 75e83876

Makefile

+1 −1
Original line number Original line Diff line number Diff line 
VERSION = 4

VERSION = 4

PATCHLEVEL = 13

PATCHLEVEL = 13

SUBLEVEL = 0

SUBLEVEL = 0

EXTRAVERSION = -rc6

EXTRAVERSION = -rc7

NAME = Fearless Coyote

NAME = Fearless Coyote





# *DOCUMENTATION*

# *DOCUMENTATION*

arch/arc/kernel/intc-arcv2.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -75,12 +75,19 @@ void arc_init_IRQ(void) 
	 * Set a default priority for all available interrupts to prevent

	 * Set a default priority for all available interrupts to prevent

	 * switching of register banks if Fast IRQ and multiple register banks

	 * switching of register banks if Fast IRQ and multiple register banks

	 * are supported by CPU.

	 * are supported by CPU.

	 * Also disable all IRQ lines so faulty external hardware won't

	 * Also disable private-per-core IRQ lines so faulty external HW won't

	 * trigger interrupt that kernel is not ready to handle.

	 * trigger interrupt that kernel is not ready to handle.

	 */

	 */

	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {

	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {

		write_aux_reg(AUX_IRQ_SELECT, i);

		write_aux_reg(AUX_IRQ_SELECT, i);

		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);

		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);



		/*

		 * Only mask cpu private IRQs here.

		 * "common" interrupts are masked at IDU, otherwise it would

		 * need to be unmasked at each cpu, with IPIs

		 */

		if (i < FIRST_EXT_IRQ)

			write_aux_reg(AUX_IRQ_ENABLE, 0);

			write_aux_reg(AUX_IRQ_ENABLE, 0);

	}

	}

arch/arc/kernel/intc-compact.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -27,7 +27,7 @@ 
 */

 */

void arc_init_IRQ(void)

void arc_init_IRQ(void)

{

{

	int level_mask = 0, i;

	unsigned int level_mask = 0, i;





       /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */

       /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */

	level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;

	level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;

arch/c6x/configs/dsk6455_defconfig

+0 −2
Original line number Original line Diff line number Diff line 
CONFIG_SOC_TMS320C6455=y

CONFIG_SOC_TMS320C6455=y

CONFIG_EXPERIMENTAL=y

# CONFIG_LOCALVERSION_AUTO is not set

# CONFIG_LOCALVERSION_AUTO is not set

CONFIG_SYSVIPC=y

CONFIG_SYSVIPC=y

CONFIG_SPARSE_IRQ=y

CONFIG_SPARSE_IRQ=y
@@ -25,7 +24,6 @@ CONFIG_BLK_DEV_LOOP=y 
CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM_COUNT=2

CONFIG_BLK_DEV_RAM_COUNT=2

CONFIG_BLK_DEV_RAM_SIZE=17000

CONFIG_BLK_DEV_RAM_SIZE=17000

CONFIG_MISC_DEVICES=y

# CONFIG_INPUT is not set

# CONFIG_INPUT is not set

# CONFIG_SERIO is not set

# CONFIG_SERIO is not set

# CONFIG_VT is not set

# CONFIG_VT is not set

arch/c6x/configs/evmc6457_defconfig

+0 −2
Original line number Original line Diff line number Diff line 
CONFIG_SOC_TMS320C6457=y

CONFIG_SOC_TMS320C6457=y

CONFIG_EXPERIMENTAL=y

# CONFIG_LOCALVERSION_AUTO is not set

# CONFIG_LOCALVERSION_AUTO is not set

CONFIG_SYSVIPC=y

CONFIG_SYSVIPC=y

CONFIG_SPARSE_IRQ=y

CONFIG_SPARSE_IRQ=y
@@ -26,7 +25,6 @@ CONFIG_BLK_DEV_LOOP=y 
CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM_COUNT=2

CONFIG_BLK_DEV_RAM_COUNT=2

CONFIG_BLK_DEV_RAM_SIZE=17000

CONFIG_BLK_DEV_RAM_SIZE=17000

CONFIG_MISC_DEVICES=y

# CONFIG_INPUT is not set

# CONFIG_INPUT is not set

# CONFIG_SERIO is not set

# CONFIG_SERIO is not set

# CONFIG_VT is not set

# CONFIG_VT is not set