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Commit dfdb3eb5 authored by Yunhui Cui's avatar Yunhui Cui Committed by Cyrille Pitchen
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mtd:fsl-quadspi:use the property fields of SPI-NOR 



We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().

Signed-off-by: default avatarYunhui Cui <B56489@freescale.com>
Signed-off-by: default avatarYunhui Cui <yunhui.cui@nxp.com>
Acked-by: default avatarHan xu <han.xu@nxp.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
parent e9cf64de

drivers/mtd/spi-nor/fsl-quadspi.c

+12 −28
Original line number Diff line number Diff line
@@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) 
	void __iomem *base = q->iobase;

	int rxfifo = q->devtype_data->rxfifo;

	u32 lut_base;

	u8 cmd, addrlen, dummy;

	int i;



	struct spi_nor *nor = &q->nor[0];

	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;

	u8 read_op = nor->read_opcode;

	u8 read_dm = nor->read_dummy;



	fsl_qspi_unlock_lut(q);



	/* Clear all the LUT table */
@@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) 
	/* Quad Read */

	lut_base = SEQID_QUAD_READ * 4;



	if (q->nor_size <= SZ_16M) {

		cmd = SPINOR_OP_READ_1_1_4;

		addrlen = ADDR24BIT;

		dummy = 8;

	} else {

		/* use the 4-byte address */

		cmd = SPINOR_OP_READ_1_1_4;

		addrlen = ADDR32BIT;

		dummy = 8;

	}



	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),

	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),

			base + QUADSPI_LUT(lut_base));

	qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),

	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |

		    LUT1(FSL_READ, PAD4, rxfifo),

			base + QUADSPI_LUT(lut_base + 1));



	/* Write enable */
@@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) 
	/* Page Program */

	lut_base = SEQID_PP * 4;



	if (q->nor_size <= SZ_16M) {

		cmd = SPINOR_OP_PP;

		addrlen = ADDR24BIT;

	} else {

		/* use the 4-byte address */

		cmd = SPINOR_OP_PP;

		addrlen = ADDR32BIT;

	}



	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),

	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |

		    LUT1(ADDR, PAD1, addrlen),

			base + QUADSPI_LUT(lut_base));

	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),

			base + QUADSPI_LUT(lut_base + 1));
@@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) 
	/* Erase a sector */

	lut_base = SEQID_SE * 4;



	cmd = q->nor[0].erase_opcode;

	addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;



	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),

	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |

		    LUT1(ADDR, PAD1, addrlen),

			base + QUADSPI_LUT(lut_base));



	/* Erase the whole chip */