Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dfcf02cd authored by Miaoqing Pan's avatar Miaoqing Pan Committed by Kalle Valo
Browse files

ath9k: fix BTCoex access invalid registers for SOC chips 



The registers of AR_GPIO_INPUT_MUX1 and AR_GPIO_PDPU were removed
from SOC chips, fix invalid accessing

Signed-off-by: default avatarMiaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 668ae0a3

drivers/net/wireless/ath/ath9k/btcoex.c

+15 −12
Original line number Original line Diff line number Diff line
@@ -162,6 +162,7 @@ void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah) 
		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);

		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);





	/* Set input mux for bt_active to gpio pin */

	/* Set input mux for bt_active to gpio pin */

	if (!AR_SREV_SOC(ah))

		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

			      AR_GPIO_INPUT_MUX1_BT_ACTIVE,

			      AR_GPIO_INPUT_MUX1_BT_ACTIVE,

			      btcoex_hw->btactive_gpio);

			      btcoex_hw->btactive_gpio);
@@ -183,13 +184,14 @@ void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah) 




	/* Set input mux for bt_prority_async and

	/* Set input mux for bt_prority_async and

	 *                  bt_active_async to GPIO pins */

	 *                  bt_active_async to GPIO pins */

	if (!AR_SREV_SOC(ah)) {

		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

			      AR_GPIO_INPUT_MUX1_BT_ACTIVE,

			      AR_GPIO_INPUT_MUX1_BT_ACTIVE,

			      btcoex_hw->btactive_gpio);

			      btcoex_hw->btactive_gpio);



		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

		REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,

			      AR_GPIO_INPUT_MUX1_BT_PRIORITY,

			      AR_GPIO_INPUT_MUX1_BT_PRIORITY,

			      btcoex_hw->btpriority_gpio);

			      btcoex_hw->btpriority_gpio);

	}





	/* Configure the desired GPIO ports for input */

	/* Configure the desired GPIO ports for input */

	ath9k_hw_gpio_request_in(ah, btcoex_hw->btactive_gpio,

	ath9k_hw_gpio_request_in(ah, btcoex_hw->btactive_gpio,
@@ -285,13 +287,13 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah, 
				 txprio_shift[i-1]);

				 txprio_shift[i-1]);

		}

		}

	}

	}



	/* Last WLAN weight has to be adjusted wrt tx priority */

	/* Last WLAN weight has to be adjusted wrt tx priority */

	if (concur_tx) {

	if (concur_tx) {

		btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);

		btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);

		btcoex_hw->wlan_weight[i-1] |= (btcoex_hw->tx_prio[stomp_type]

		btcoex_hw->wlan_weight[i-1] |= (btcoex_hw->tx_prio[stomp_type]

						      << txprio_shift[i-1]);

						      << txprio_shift[i-1]);

	}

	}



}

}

EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);

EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
@@ -375,7 +377,8 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah) 
		break;

		break;

	}

	}





	if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_MCI) {

	if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_MCI &&

	    !AR_SREV_SOC(ah)) {

		REG_RMW(ah, AR_GPIO_PDPU,

		REG_RMW(ah, AR_GPIO_PDPU,

			(0x2 << (btcoex_hw->btactive_gpio * 2)),

			(0x2 << (btcoex_hw->btactive_gpio * 2)),

			(0x3 << (btcoex_hw->btactive_gpio * 2)));

			(0x3 << (btcoex_hw->btactive_gpio * 2)));