Loading arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +0 −16 Original line number Diff line number Diff line Loading @@ -37,8 +37,6 @@ clock-max-rate = <0 0 0 307000000 19200000 307000000>; qcom,dss-cx-ipeak = <&cx_ipeak_lm 3>; sde-vdd-supply = <&mdss_core_gdsc>; /* interrupt config */ interrupts = <0 83 0>; interrupt-controller; Loading Loading @@ -211,20 +209,6 @@ qcom,sde-dspp-dither = <0x82c 0x00010007>; }; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "sde-vdd"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; Loading Loading
arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +0 −16 Original line number Diff line number Diff line Loading @@ -37,8 +37,6 @@ clock-max-rate = <0 0 0 307000000 19200000 307000000>; qcom,dss-cx-ipeak = <&cx_ipeak_lm 3>; sde-vdd-supply = <&mdss_core_gdsc>; /* interrupt config */ interrupts = <0 83 0>; interrupt-controller; Loading Loading @@ -211,20 +209,6 @@ qcom,sde-dspp-dither = <0x82c 0x00010007>; }; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "sde-vdd"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; Loading