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Commit df61bc70 authored by Mukesh Kumar Savaliya's avatar Mukesh Kumar Savaliya Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add QUPV3 SE dt nodes for uart on trinket 



Add initial device tree node for QUPV3 uart instances to support
serial console and BT used HSUART.

Change-Id: Ice89677ec87c0f095654b864c2e1c1291ea05eb3
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent a487c3ab

arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi

+97 −0
Original line number Diff line number Diff line
@@ -311,5 +311,102 @@ 
				};

			};

		};



		qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {

			qupv3_se3_rx: qupv3_se3_rx {

				mux {

					pins = "gpio15";

					function = "qup03";

				};



				config {

					pins = "gpio15";

					drive-strength = <2>;

					bias-no-pull;

				};

			};



			qupv3_se3_tx: qupv3_se6_tx {

				mux {

					pins = "gpio14";

					function = "qup03";

				};



				config {

					pins = "gpio14";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {

			qupv3_se4_2uart_active: qupv3_se4_2uart_active {

				mux {

					pins = "gpio16", "gpio17";

					function = "qup04";

				};



				config {

						pins = "gpio16", "gpio17";

						drive-strength = <2>;

						bias-disable;

				};

			};



			qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {

				mux {

						pins = "gpio16", "gpio17";

						function = "gpio";

				};



				config {

						pins = "gpio16", "gpio17";

						drive-strength = <2>;

						bias-pull-down;

				};

			};

		};



		qupv3_se9_4uart_pins: qupv3_se9_4uart_pins {

			qupv3_se9_ctsrx: qupv3_se9_ctsrx {

				mux {

					pins = "gpio10", "gpio13";

					function = "qup14";

				};



				config {

					pins = "gpio10", "gpio13";

					drive-strength = <2>;

					bias-no-pull;

				};

			};



			qupv3_se9_rts: qupv3_se9_rts {

				mux {

					pins = "gpio11";

					function = "qup14";

				};



				config {

					pins = "gpio11";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se9_tx: qupv3_se9_tx {

				mux {

					pins = "gpio12";

					function = "qup14";

				};



				config {

					pins = "gpio12";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};

	};

};

arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi

+264 −205
Original line number Diff line number Diff line
@@ -41,6 +41,42 @@ 
		};

	};



	/* HSUART with 2-wire mode */

	qupv3_se3_4uart: qcom,qup_uart@0x4a8c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4a8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se3_tx>, <&qupv3_se3_rx>;

		pinctrl-1 = <&qupv3_se3_tx>, <&qupv3_se3_rx>;

		interrupts-extended = <&intc GIC_SPI 330 0>,

			<&tlmm 15 0>;

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* Debug UART Instance for CDP/MTP/RUMI platform */

	qupv3_se4_2uart: qcom,qup_uart@0x4a90000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x4a90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_active>;

		pinctrl-1 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 331 0>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se0_i2c: i2c@4a80000 {

		compatible = "qcom,i2c-geni";
@@ -156,6 +192,30 @@ 
		};

	};



	/*

	 * HS UART instances. HS UART usecases can be supported on these

	 * instances only.

	 */

	qupv3_se9_4uart: qcom,qup_uart@0x4c90000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4c90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_ctsrx>, <&qupv3_se9_rts>,

			<&qupv3_se9_tx>;

		pinctrl-1 = <&qupv3_se9_ctsrx>, <&qupv3_se9_rts>,

			<&qupv3_se9_tx>;

		interrupts-extended = <&intc GIC_SPI 312 0>,

			<&tlmm 13 0>;

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se5_i2c: i2c@4c80000 {

		compatible = "qcom,i2c-geni";
@@ -256,5 +316,4 @@ 
		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



};

arch/arm64/boot/dts/qcom/trinket-rumi.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -45,6 +45,10 @@ 
	};

};



&qupv3_se4_2uart {

	status = "ok";

};



&usb0 {

	/delete-property/ extcon;

	dwc3@4e00000 {

arch/arm64/boot/dts/qcom/trinket.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ 
	qcom,msm-id = <394 0x0>;

	interrupt-parent = <&intc>;



	aliases {

		serial0 = &qupv3_se4_2uart;

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;
@@ -1222,8 +1226,10 @@ 
		cell-index = <0>;

	};

};



#include "pmi632.dtsi"

#include "pm6125.dtsi"

#include "trinket-qupv3.dtsi"

#include "trinket-pinctrl.dtsi"

#include "trinket-ion.dtsi"

#include "pm6125-rpm-regulator.dtsi"