Merge "msm: kgsl: Restore aperture registers on SDM855v1" into msm-4.14 (deee853a) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/msm/adreno.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -1681,6 +1681,15 @@ static int _adreno_start(struct adreno_device *adreno_dev)
		if (regulator_left_on)
		_soft_reset(adreno_dev);

		if ((adreno_is_a640v1(adreno_dev)) &&
		scm_is_call_available(SCM_SVC_MP, CP_SMMU_APERTURE_ID)) {
		ret = kgsl_program_smmu_aperture();
		if (ret) {
		pr_err("SMMU aperture programming call failed with error %d\n",
		ret);
		goto error_pwr_off;
		}
		}
		adreno_ringbuffer_set_global(adreno_dev, 0);

		status = kgsl_mmu_start(device);

+6 −0

Original line number	Diff line number	Diff line
		@@ -1266,6 +1266,12 @@ static inline int adreno_is_a630v2(struct adreno_device *adreno_dev)
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1);
		}

		static inline int adreno_is_a640v1(struct adreno_device *adreno_dev)
		{
		return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A640) &&
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);
		}

		/*
		* adreno_checkreg_off() - Checks the validity of a register enum
		* @adreno_dev: Pointer to adreno device

+6 −8

Original line number	Diff line number	Diff line
		@@ -34,9 +34,6 @@
		#include "kgsl_trace.h"
		#include "kgsl_pwrctrl.h"

		#define CP_APERTURE_REG 0
		#define CP_SMMU_APERTURE_ID 0x1B

		#define _IOMMU_PRIV(_mmu) (&((_mmu)->priv.iommu))

		#define ADDR_IN_GLOBAL(_mmu, _a) \
		@@ -117,7 +114,7 @@ static int global_pt_count;
		uint64_t global_pt_alloc;
		static struct kgsl_memdesc gpu_qdss_desc;
		static struct kgsl_memdesc gpu_qtimer_desc;

		static unsigned int context_bank_number;
		void kgsl_print_global_pt_entries(struct seq_file *s)
		{
		int i;
		@@ -1168,11 +1165,12 @@ void _enable_gpuhtw_llc(struct kgsl_mmu mmu, struct kgsl_iommu_pt iommu_pt)
		"System cache not enabled for GPU pagetable walks: %d\n", ret);
		}

		static int program_smmu_aperture(unsigned int cb, unsigned int aperture_reg)
		int kgsl_program_smmu_aperture(void)
		{
		struct scm_desc desc = {0};

		desc.args[0] = 0xFFFF0000 \| ((aperture_reg & 0xff) << 8) \| (cb & 0xff);
		desc.args[0] = 0xFFFF0000 \| ((CP_APERTURE_REG & 0xff) << 8) \|
		(context_bank_number & 0xff);
		desc.args[1] = 0xFFFFFFFF;
		desc.args[2] = 0xFFFFFFFF;
		desc.args[3] = 0xFFFFFFFF;
		@@ -1220,10 +1218,10 @@ static int _init_global_pt(struct kgsl_mmu mmu, struct kgsl_pagetable pt)
		ret);
		goto done;
		}

		context_bank_number = cb_num;
		if (!MMU_FEATURE(mmu, KGSL_MMU_GLOBAL_PAGETABLE) &&
		scm_is_call_available(SCM_SVC_MP, CP_SMMU_APERTURE_ID)) {
		ret = program_smmu_aperture(cb_num, CP_APERTURE_REG);
		ret = kgsl_program_smmu_aperture();
		if (ret) {
		pr_err("SMMU aperture programming call failed with error %d\n",
		ret);

+5 −1

Original line number	Diff line number	Diff line
		@@ -49,7 +49,8 @@
		*/
		#define KGSL_IOMMU_SVM_BASE64 0x700000000ULL
		#define KGSL_IOMMU_SVM_END64 0x800000000ULL

		#define CP_APERTURE_REG 0
		#define CP_SMMU_APERTURE_ID 0x1B
		/* TLBSTATUS register fields */
		#define KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE BIT(0)

		@@ -197,6 +198,9 @@ kgsl_iommu_reg(struct kgsl_iommu_context *ctx, enum kgsl_iommu_reg_map reg)
		return ctx->regbase + kgsl_iommu_reg_list[reg];
		}

		/* Program aperture registers using SCM call */
		int kgsl_program_smmu_aperture(void);

		#define KGSL_IOMMU_SET_CTX_REG_Q(_ctx, REG, val) \
		writeq_relaxed((val), \
		kgsl_iommu_reg((_ctx), KGSL_IOMMU_CTX_##REG))