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Commit deed9deb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'powerpc-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 

Pull powerpc fixes from Michael Ellerman:
 "Nothing that really stands out, just a bunch of fixes that have come
  in in the last couple of weeks.

  None of these are actually fixes for code that is new in 4.13. It's
  roughly half older bugs, with fixes going to stable, and half
  fixes/updates for Power9.

  Thanks to: Aneesh Kumar K.V, Anton Blanchard, Balbir Singh, Benjamin
  Herrenschmidt, Madhavan Srinivasan, Michael Neuling, Nicholas Piggin,
  Oliver O'Halloran"

* tag 'powerpc-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/64: Fix atomic64_inc_not_zero() to return an int
  powerpc: Fix emulation of mfocrf in emulate_step()
  powerpc: Fix emulation of mcrf in emulate_step()
  powerpc/perf: Add POWER9 alternate PM_RUN_CYC and PM_RUN_INST_CMPL events
  powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9
  powerpc/asm: Mark cr0 as clobbered in mftb()
  powerpc/powernv: Fix local TLB flush for boot and MCE on POWER9
  powerpc/mm/radix: Synchronize updates to the process table
  powerpc/mm/radix: Properly clear process table entry
  powerpc/powernv: Tell OPAL about our MMU mode on POWER9
  powerpc/kexec: Fix radix to hash kexec due to IAMR/AMOR
parents ccd5d1b9 01e6a61a

arch/powerpc/include/asm/atomic.h

+2 −2
Original line number Diff line number Diff line
@@ -560,7 +560,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) 
 * Atomically increments @v by 1, so long as @v is non-zero.

 * Returns non-zero if @v was non-zero, and zero otherwise.

 */

static __inline__ long atomic64_inc_not_zero(atomic64_t *v)

static __inline__ int atomic64_inc_not_zero(atomic64_t *v)

{

	long t1, t2;
@@ -579,7 +579,7 @@ static __inline__ long atomic64_inc_not_zero(atomic64_t *v) 
	: "r" (&v->counter)

	: "cc", "xer", "memory");



	return t1;

	return t1 != 0;

}



#endif /* __powerpc64__ */

arch/powerpc/include/asm/opal-api.h

+9 −0
Original line number Diff line number Diff line
@@ -876,6 +876,15 @@ struct OpalIoPhb4ErrorData { 
enum {

	OPAL_REINIT_CPUS_HILE_BE	= (1 << 0),

	OPAL_REINIT_CPUS_HILE_LE	= (1 << 1),



	/* These two define the base MMU mode of the host on P9

	 *

	 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still

	 * create hash guests in "radix" mode with care (full core

	 * switch only).

	 */

	OPAL_REINIT_CPUS_MMU_HASH	= (1 << 2),

	OPAL_REINIT_CPUS_MMU_RADIX	= (1 << 3),

};



typedef struct oppanel_line {

arch/powerpc/include/asm/reg.h

+1 −1
Original line number Diff line number Diff line
@@ -1303,7 +1303,7 @@ static inline void msr_check_and_clear(unsigned long bits) 
				"	.llong 0\n"			\

				".previous"				\

			: "=r" (rval) \

			: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \

			: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \

			rval;})

#else

#define mftb()		({unsigned long rval;	\

arch/powerpc/kernel/cpu_setup_power.S

+10 −3
Original line number Diff line number Diff line
@@ -218,13 +218,20 @@ __init_tlb_power8: 
	ptesync

1:	blr



/*

 * Flush the TLB in hash mode. Hash must flush with RIC=2 once for process

 * and one for partition scope to clear process and partition table entries.

 */

__init_tlb_power9:

	li	r6,POWER9_TLB_SETS_HASH

	li	r6,POWER9_TLB_SETS_HASH - 1

	mtctr	r6

	li	r7,0xc00	/* IS field = 0b11 */

	li	r8,0

	ptesync

2:	tlbiel	r7

	addi	r7,r7,0x1000

	PPC_TLBIEL(7, 8, 2, 1, 0)

	PPC_TLBIEL(7, 8, 2, 0, 0)

2:	addi	r7,r7,0x1000

	PPC_TLBIEL(7, 8, 0, 0, 0)

	bdnz	2b

	ptesync

1:	blr

arch/powerpc/kernel/dt_cpu_ftrs.c

+2 −14
Original line number Diff line number Diff line
@@ -94,9 +94,6 @@ static void (*init_pmu_registers)(void); 


static void cpufeatures_flush_tlb(void)

{

	unsigned long rb;

	unsigned int i, num_sets;



	/*

	 * This is a temporary measure to keep equivalent TLB flush as the

	 * cputable based setup code.
@@ -105,24 +102,15 @@ static void cpufeatures_flush_tlb(void) 
	case PVR_POWER8:

	case PVR_POWER8E:

	case PVR_POWER8NVL:

		num_sets = POWER8_TLB_SETS;

		__flush_tlb_power8(POWER8_TLB_SETS);

		break;

	case PVR_POWER9:

		num_sets = POWER9_TLB_SETS_HASH;

		__flush_tlb_power9(POWER9_TLB_SETS_HASH);

		break;

	default:

		num_sets = 1;

		pr_err("unknown CPU version for boot TLB flush\n");

		break;

	}



	asm volatile("ptesync" : : : "memory");

	rb = TLBIEL_INVAL_SET;

	for (i = 0; i < num_sets; i++) {

		asm volatile("tlbiel %0" : : "r" (rb));

		rb += 1 << TLBIEL_INVAL_SET_SHIFT;

	}

	asm volatile("ptesync" : : : "memory");

}



static void __restore_cpu_cpufeatures(void)