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Commit deca1d1f authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Add GRBM lock to various SI functions 



Add missing lock around SE/SH/INSTANCE selections.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 48fad3af

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+8 −0
Original line number Diff line number Diff line
@@ -946,6 +946,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 
	u32 disabled_rbs = 0;

	u32 enabled_rbs = 0;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < se_num; i++) {

		for (j = 0; j < sh_per_se; j++) {

			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -954,6 +955,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 
		}

	}

	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	mutex_unlock(&adev->grbm_idx_mutex);



	mask = 1;

	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
@@ -965,6 +967,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 
	adev->gfx.config.backend_enable_mask = enabled_rbs;

	adev->gfx.config.num_rbs = hweight32(enabled_rbs);



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < se_num; i++) {

		gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);

		data = 0;
@@ -986,6 +989,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 
		WREG32(PA_SC_RASTER_CONFIG, data);

	}

	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	mutex_unlock(&adev->grbm_idx_mutex);

}

/*

static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
@@ -1017,6 +1021,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, 
	u32 data, mask;

	u32 active_cu = 0;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < se_num; i++) {

		for (j = 0; j < sh_per_se; j++) {

			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -1035,6 +1040,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, 
		}

	}

	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	mutex_unlock(&adev->grbm_idx_mutex);

}



static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
@@ -2475,10 +2481,12 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev, 
	u32 mask = 0, tmp, tmp1;

	int i;



	mutex_lock(&adev->grbm_idx_mutex);

	gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);

	tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

	tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);

	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	mutex_unlock(&adev->grbm_idx_mutex);



	tmp &= 0xffff0000;