Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (deb79d5e) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+0 −14

Original line number	Diff line number	Diff line
		@@ -400,13 +400,6 @@

		/* PHY TIMINGS REVISION P */
		&dsi_dual_nt35597_truly_video {
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-on-check-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -464,13 +457,6 @@
		};

		&dsi_sharp_4k_dsc_video {
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
		qcom,mdss-dsi-panel-status-value = <0x7>;
		qcom,mdss-dsi-panel-on-check-value = <0x7>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,mdss-dsi-display-timings {
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08

drivers/gpu/drm/msm/dp/dp_display.c

+5 −9

Original line number	Diff line number	Diff line
		@@ -829,11 +829,6 @@ static void dp_display_attention_work(struct work_struct *work)
		if (!dp->power_on)
		goto mst_attention;

		if (dp_display_is_hdcp_enabled(dp) && dp->hdcp.ops->cp_irq) {
		if (!dp->hdcp.ops->cp_irq(dp->hdcp.data))
		goto mst_attention;
		}

		if (dp->link->sink_request & DS_PORT_STATUS_CHANGED) {
		dp_display_handle_disconnect(dp);

		@@ -861,16 +856,17 @@ static void dp_display_attention_work(struct work_struct *work)
		goto mst_attention;
		}

		if (dp->link->sink_request & DP_LINK_STATUS_UPDATED) {
		if (dp->link->sink_request & DP_TEST_LINK_TRAINING) {
		dp->link->send_test_response(dp->link);
		dp_display_handle_maintenance_req(dp);
		goto mst_attention;
		}

		if (dp->link->sink_request & DP_TEST_LINK_TRAINING) {
		dp->link->send_test_response(dp->link);
		if (dp->link->sink_request & DP_LINK_STATUS_UPDATED)
		dp_display_handle_maintenance_req(dp);
		}

		if (dp_display_is_hdcp_enabled(dp) && dp->hdcp.ops->cp_irq)
		dp->hdcp.ops->cp_irq(dp->hdcp.data);
		mst_attention:
		dp_display_mst_attention(dp);
		}

drivers/gpu/drm/msm/sde/sde_plane.c

+16 −18

Original line number	Diff line number	Diff line
		@@ -1077,23 +1077,26 @@ static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
		}

		static void _sde_plane_setup_scaler3(struct sde_plane *psde,
		struct sde_plane_state *pstate,
		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
		struct sde_hw_scaler3_cfg *scale_cfg,
		const struct sde_format *fmt,
		struct sde_plane_state pstate, const struct sde_format fmt,
		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
		{
		uint32_t decimated, i;
		uint32_t decimated, i, src_w, src_h, dst_w, dst_h;
		struct sde_hw_scaler3_cfg *scale_cfg;

		if (!psde \|\| !pstate \|\| !scale_cfg \|\| !fmt \|\| !chroma_subsmpl_h \|\|
		!chroma_subsmpl_v) {
		SDE_ERROR(
		"psde %d pstate %d scale_cfg %d fmt %d smp_h %d smp_v %d\n",
		!!psde, !!pstate, !!scale_cfg, !!fmt, chroma_subsmpl_h,
		if (!psde \|\| !pstate \|\| !fmt \|\|
		!chroma_subsmpl_h \|\| !chroma_subsmpl_v) {
		SDE_ERROR("psde %d pstate %d fmt %d smp_h %d smp_v %d\n",
		!!psde, !!pstate, !!fmt, chroma_subsmpl_h,
		chroma_subsmpl_v);
		return;
		}

		scale_cfg = &pstate->scaler3_cfg;
		src_w = psde->pipe_cfg.src_rect.w;
		src_h = psde->pipe_cfg.src_rect.h;
		dst_w = psde->pipe_cfg.dst_rect.w;
		dst_h = psde->pipe_cfg.dst_rect.h;

		memset(scale_cfg, 0, sizeof(*scale_cfg));
		memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));

		@@ -1501,12 +1504,7 @@ static void _sde_plane_setup_scaler(struct sde_plane *psde,
		if (rc \|\| pstate->scaler_check_state !=
		SDE_PLANE_SCLCHECK_SCALER_V2) {
		/* calculate default config for QSEED3 */
		_sde_plane_setup_scaler3(psde, pstate,
		psde->pipe_cfg.src_rect.w,
		psde->pipe_cfg.src_rect.h,
		psde->pipe_cfg.dst_rect.w,
		psde->pipe_cfg.dst_rect.h,
		&pstate->scaler3_cfg, fmt,
		_sde_plane_setup_scaler3(psde, pstate, fmt,
		chroma_subsmpl_h, chroma_subsmpl_v);
		}
		} else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 \|\|