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Commit dea54fba authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by Ralf Baechle
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phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module 



This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.

Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Acked-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Cc: martin.blumenstingl@googlemail.com
Cc: john@phrozen.org
Cc: andy.shevchenko@gmail.com
Cc: p.zabel@pengutronix.de
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17127/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d5103604

Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt

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+40 −0
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Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding

===========================================



This binding describes the USB PHY hardware provided by the RCU module on the

Lantiq XWAY SoCs.



This node has to be a sub node of the Lantiq RCU block.



-------------------------------------------------------------------------------

Required properties (controller (parent) node):

- compatible	: Should be one of

			"lantiq,ase-usb2-phy"

			"lantiq,danube-usb2-phy"

			"lantiq,xrx100-usb2-phy"

			"lantiq,xrx200-usb2-phy"

			"lantiq,xrx300-usb2-phy"

- reg		: Defines the following sets of registers in the parent

		  syscon device

			- Offset of the USB PHY configuration register

			- Offset of the USB Analog configuration

			  register (only for xrx200 and xrx200)

- clocks	: References to the (PMU) "phy" clk gate.

- clock-names	: Must be "phy"

- resets	: References to the RCU USB configuration reset bits.

- reset-names	: Must be one of the following:

			"phy" (optional)

			"ctrl" (shared)



-------------------------------------------------------------------------------

Example for the USB PHYs on an xRX200 SoC:

	usb_phy0: usb2-phy@18 {

		compatible = "lantiq,xrx200-usb2-phy";

		reg = <0x18 4>, <0x38 4>;



		clocks = <&pmu PMU_GATE_USB0_PHY>;

		clock-names = "phy";

		resets = <&reset1 4 4>, <&reset0 4 4>;

		reset-names = "phy", "ctrl";

		#phy-cells = <0>;

	};

arch/mips/lantiq/xway/sysctrl.c

+18 −18
Original line number Diff line number Diff line
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void) 


	if (of_machine_is_compatible("lantiq,grx390") ||

	    of_machine_is_compatible("lantiq,ar10")) {

		clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);

		clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);

		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);

		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);

		/* rc 0 */

		clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);

		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void) 
		else

			clkdev_add_static(CLOCK_133M, CLOCK_133M,

						CLOCK_133M, CLOCK_133M);

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);

		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);

		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);

		clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -500,8 +500,8 @@ void __init ltq_soc_init(void) 
	} else if (of_machine_is_compatible("lantiq,grx390")) {

		clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),

				  ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);

		/* rc 2 */

		clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);

		clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
@@ -513,8 +513,8 @@ void __init ltq_soc_init(void) 
	} else if (of_machine_is_compatible("lantiq,ar10")) {

		clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),

				  ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |

			       PMU_PPE_DP | PMU_PPE_TC);

		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
@@ -526,10 +526,10 @@ void __init ltq_soc_init(void) 
	} else if (of_machine_is_compatible("lantiq,vr9")) {

		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),

				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());

		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);

		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);

		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);

		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);

		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);

		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);

		clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);

		clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);

		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -550,10 +550,10 @@ void __init ltq_soc_init(void) 
	} else if (of_machine_is_compatible("lantiq,ar9")) {

		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),

				ltq_ar9_fpi_hz(), CLOCK_250M);

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);

		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);

		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);

		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);

		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);

		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
@@ -562,8 +562,8 @@ void __init ltq_soc_init(void) 
	} else {

		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),

				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());

		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);

		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);

		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);

		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);

		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);

drivers/phy/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ source "drivers/phy/allwinner/Kconfig" 
source "drivers/phy/amlogic/Kconfig"

source "drivers/phy/broadcom/Kconfig"

source "drivers/phy/hisilicon/Kconfig"

source "drivers/phy/lantiq/Kconfig"

source "drivers/phy/marvell/Kconfig"

source "drivers/phy/motorola/Kconfig"

source "drivers/phy/qualcomm/Kconfig"

drivers/phy/Makefile

+1 −1
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@@ -7,9 +7,9 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o 
obj-$(CONFIG_PHY_MT65XX_USB3)		+= phy-mt65xx-usb3.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o



obj-$(CONFIG_ARCH_SUNXI)		+= allwinner/

obj-$(CONFIG_ARCH_MESON)		+= amlogic/

obj-$(CONFIG_LANTIQ)			+= lantiq/

obj-$(CONFIG_ARCH_RENESAS)		+= renesas/

obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/

obj-$(CONFIG_ARCH_TEGRA)		+= tegra/

drivers/phy/lantiq/Kconfig

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+9 −0
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#

# Phy drivers for Lantiq / Intel platforms

#

config PHY_LANTIQ_RCU_USB2

	tristate "Lantiq XWAY SoC RCU based USB PHY"

	depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)

	select GENERIC_PHY

	help

	  Support for the USB PHY(s) on the Lantiq / Intel XWAY family SoCs.