Snapshot commit for serial peripheral drivers.

GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)

								I2C controller

Required properties:

 - compatible: Should be:

   * "qcom,i2c-geni.

 - reg: Should contain QUP register address and length.

 - interrupts: Should contain I2C interrupt.

 - clocks: Serial engine core clock, and AHB clocks needed by the device.

 - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

   should be "active" and "sleep" for the pin confuguration when core is active

   or when entering sleep state.

 - #address-cells: Should be <1> Address cells for i2c device address

 - #size-cells: Should be <0> as i2c addresses have no size component

 - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.

Optional property:

 - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.

   When missing default to 400000Hz.

Child nodes should conform to i2c bus binding.

Example:

i2c@a94000 {

	compatible = "qcom,i2c-geni";

	reg = <0xa94000 0x4000>;

	interrupts = <GIC_SPI 358 0>;

	clock-names = "se-clk", "m-ahb", "s-ahb";

	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_i2c_5_active>;

	pinctrl-1 = <&qup_1_i2c_5_sleep>;

	#address-cells = <1>;

	#size-cells = <0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,clk-freq-out = <400000>;

};

GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)

The QUP v3 core is a GENI based AHB slave that provides a common data path

(an output FIFO and an input FIFO) for serial peripheral interface (SPI)

mini-core.

SPI in master mode supports up to 50MHz, up to four chip selects, programmable

data path from 4 bits to 32 bits and numerous protocol variants.

Required properties:

- compatible:	  Should contain "qcom,spi-geni"

- reg:		  Should contain base register location and length

- interrupts:	  Interrupt number used by this controller

- clocks:	  Should contain the core clock and the AHB clock.

- clock-names:	  Should be "core" for the core clock and "iface" for the

		  AHB clock.

- pinctrl-names:  Property should contain "default" and "sleep" for the

		  pin configurations during the usecase and during idle.

- pinctrl-x:	  phandle to the default/sleep pin configurations.

- #address-cells: Number of cells required to define a chip select

		  address on the SPI bus. Should be set to 1.

- #size-cells:	  Should be zero.

- spi-max-frequency: Specifies maximum SPI clock frequency,

		     Units - Hz. Definition as per

		     Documentation/devicetree/bindings/spi/spi-bus.txt

- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller.

Optional properties:

- qcom,rt:	Specifies if the framework worker thread for this

		controller device should have "real-time" priority.

SPI slave nodes must be children of the SPI master node and can contain

properties described in Documentation/devicetree/bindings/spi/spi-bus.txt

Example:

	qupv3_spi10: spi@a84000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qup_1_spi_2_active>;

		pinctrl-1 = <&qup_1_spi_2_sleep>;

		interrupts = <GIC_SPI 354 0>;

		spi-max-frequency = <19200000>;

		qcom,wrapper-core = <&qupv3_0>;

		dev@0 {

			compatible = "dummy,slave";

			reg = <0>;

			spi-max-frequency = <9600000>;

		};

	};

	  This driver can also be built as a module.  If so, the module

	  will be called i2c-qup.

config I2C_QCOM_GENI

        tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"

        depends on ARCH_QCOM

        help

          If you say yes to this option, support will be included for the

          built-in I2C interface on the Qualcomm Technologies Inc.'s SoCs.

          This driver can also be built as a module.  If so, the module

          will be called i2c-qcom-geni.

config I2C_RIIC

	tristate "Renesas RIIC adapter"

	depends on ARCH_RENESAS || COMPILE_TEST

obj-$(CONFIG_I2C_PXA)		+= i2c-pxa.o

obj-$(CONFIG_I2C_PXA_PCI)	+= i2c-pxa-pci.o

obj-$(CONFIG_I2C_QUP)		+= i2c-qup.o

obj-$(CONFIG_I2C_QCOM_GENI)     += i2c-qcom-geni.o

obj-$(CONFIG_I2C_RIIC)		+= i2c-riic.o

obj-$(CONFIG_I2C_RK3X)		+= i2c-rk3x.o

obj-$(CONFIG_I2C_S3C2410)	+= i2c-s3c2410.o