Merge "msm: kgsl: Don't reset HFI indexes on reset" (dd0f370b) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/msm/kgsl_gmu.c

+2 −4

Original line number	Diff line number	Diff line
		@@ -1508,9 +1508,8 @@ static int gmu_suspend(struct kgsl_device *device)
		return 0;

		/* Pending message in all queues are abandoned */
		hfi_stop(gmu);
		clear_bit(GMU_HFI_ON, &gmu->flags);
		gmu_dev_ops->irq_disable(device);
		hfi_stop(gmu);

		if (gmu_dev_ops->rpmh_gpu_pwrctrl(adreno_dev, GMU_SUSPEND, 0, 0))
		return -EINVAL;
		@@ -1681,9 +1680,8 @@ static void gmu_stop(struct kgsl_device *device)
		goto error;

		/* Pending message in all queues are abandoned */
		hfi_stop(gmu);
		clear_bit(GMU_HFI_ON, &gmu->flags);
		gmu_dev_ops->irq_disable(device);
		hfi_stop(gmu);

		gmu_dev_ops->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_STOP, 0, 0);
		gmu_disable_clks(gmu);

drivers/gpu/msm/kgsl_hfi.c

+30 −10

Original line number	Diff line number	Diff line
		@@ -58,6 +58,9 @@ static int hfi_queue_read(struct gmu_device *gmu, uint32_t queue_idx,
		uint32_t size;
		int result = 0;

		if (hdr->status == HFI_QUEUE_STATUS_DISABLED)
		return -EINVAL;

		if (hdr->read_index == hdr->write_index) {
		hdr->rx_req = 1;
		return -ENODATA;
		@@ -113,7 +116,7 @@ static int hfi_queue_write(struct gmu_device *gmu, uint32_t queue_idx,
		uint32_t size = MSG_HDR_GET_SIZE(*msg);
		uint32_t id = MSG_HDR_GET_ID(*msg);

		if (hdr->enabled == 0)
		if (hdr->status == HFI_QUEUE_STATUS_DISABLED)
		return -EINVAL;

		if (size > HFI_MAX_MSG_SIZE) {
		@@ -188,11 +191,12 @@ void hfi_init(struct kgsl_hfi hfi, struct gmu_memdesc mem_addr,
		struct {
		unsigned int idx;
		unsigned int pri;
		unsigned int status;
		} queue[HFI_QUEUE_MAX] = {
		{ HFI_CMD_ID, HFI_CMD_PRI },
		{ HFI_MSG_ID, HFI_MSG_PRI },
		{ HFI_DBG_ID, HFI_DBG_PRI },
		{ HFI_DSP_ID_0, HFI_DSP_PRI_0 },
		{ HFI_CMD_IDX, HFI_CMD_PRI, HFI_QUEUE_STATUS_ENABLED },
		{ HFI_MSG_IDX, HFI_MSG_PRI, HFI_QUEUE_STATUS_ENABLED },
		{ HFI_DBG_IDX, HFI_DBG_PRI, HFI_QUEUE_STATUS_ENABLED },
		{ HFI_DSP_IDX_0, HFI_DSP_PRI_0, HFI_QUEUE_STATUS_DISABLED },
		};

		/* Fill Table Header */
		@@ -209,7 +213,7 @@ void hfi_init(struct kgsl_hfi hfi, struct gmu_memdesc mem_addr,
		hdr = &tbl->qhdr[i];
		hdr->start_addr = GMU_QUEUE_START_ADDR(mem_addr, i);
		hdr->type = QUEUE_HDR_TYPE(queue[i].idx, queue[i].pri, 0, 0);
		hdr->enabled = 0x1;
		hdr->status = queue[i].status;
		hdr->queue_size = queue_sz_bytes >> 2; /* convert to dwords */
		hdr->msg_size = 0;
		hdr->drop_cnt = 0;
		@@ -639,11 +643,28 @@ int hfi_start(struct kgsl_device *device,
		struct gmu_device *gmu, uint32_t boot_state)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		int result;
		struct gmu_memdesc *mem_addr = gmu->hfi_mem;
		struct hfi_queue_table *tbl = mem_addr->hostptr;
		struct hfi_queue_header *hdr;
		int result, i;

		if (test_bit(GMU_HFI_ON, &gmu->flags))
		return 0;

		/* Force read_index to the write_index no matter what */
		for (i = 0; i < HFI_QUEUE_MAX; i++) {
		hdr = &tbl->qhdr[i];
		if (hdr->status == HFI_QUEUE_STATUS_DISABLED)
		continue;

		if (hdr->read_index != hdr->write_index) {
		dev_err(&gmu->pdev->dev,
		"HFI Q[%d] Index Error: read:0x%X write:0x%X\n",
		i, hdr->read_index, hdr->write_index);
		hdr->read_index = hdr->write_index;
		}
		}

		if (!adreno_is_a640(adreno_dev) && !adreno_is_a680(adreno_dev)) {
		result = hfi_send_gmu_init(gmu, boot_state);
		if (result)
		@@ -703,14 +724,13 @@ void hfi_stop(struct gmu_device *gmu)
		/* Flush HFI queues */
		for (i = 0; i < HFI_QUEUE_MAX; i++) {
		hdr = &tbl->qhdr[i];
		if (hdr->status == HFI_QUEUE_STATUS_DISABLED)
		continue;

		if (hdr->read_index != hdr->write_index)
		dev_err(&gmu->pdev->dev,
		"HFI queue[%d] is not empty before close: rd=%d,wt=%d",
		i, hdr->read_index, hdr->write_index);

		hdr->read_index = 0x0;
		hdr->write_index = 0x0;
		}

		clear_bit(GMU_HFI_ON, &gmu->flags);

drivers/gpu/msm/kgsl_hfi.h

+5 −2

Original line number	Diff line number	Diff line
		@@ -38,6 +38,9 @@
		#define HFI_DSP_IDX_BASE 3
		#define HFI_DSP_IDX_0 3

		#define HFI_QUEUE_STATUS_DISABLED 0
		#define HFI_QUEUE_STATUS_ENABLED 1

		/* HTOF queue priority, 1 is highest priority */
		#define HFI_CMD_PRI 10
		#define HFI_MSG_PRI 10
		@@ -128,7 +131,7 @@ struct hfi_queue_table_header {

		/**
		* struct hfi_queue_header - HFI queue header structure
		* @enabled: active: 1; inactive: 0
		* @status: active: 1; inactive: 0
		* @start_addr: starting address of the queue in GMU VA space
		* @type: queue type encoded the priority, ID and send/recevie types
		* @queue_size: size of the queue
		@@ -143,7 +146,7 @@ struct hfi_queue_table_header {
		* @write_index: write index of the queue
		*/
		struct hfi_queue_header {
		uint32_t enabled;
		uint32_t status;
		uint32_t start_addr;
		uint32_t type;
		uint32_t queue_size;