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Commit dcb8a7e2 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: gcc: Update debugcc for MCC for SDMMAGPIE 



Add support for MCC debug mux and remove some unwanted debug clocks.

Change-Id: I40aaa1ff306cd091b0bec0d85194b145a79a7643
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent a2e859ee

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+7 −1
Original line number Diff line number Diff line
@@ -719,9 +719,14 @@ 
		reg = <0x182a0018 0x4>;

	};



	mccc_debug: syscon@90b0000 {

		compatible = "syscon";

		reg = <0x90b0000 0x1000>;

	};



	clock_debug: qcom,cc-debug {

		compatible = "qcom,debugcc-sdmmagpie";

		qcom,cc-count = <7>;

		qcom,cc-count = <8>;

		qcom,gcc = <&clock_gcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,camcc = <&clock_camcc>;
@@ -729,6 +734,7 @@ 
		qcom,gpucc = <&clock_gpucc>;

		qcom,npucc = <&clock_npucc>;

		qcom,cpucc = <&cpucc_debug>;

		qcom,mccc = <&mccc_debug>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "xo_clk_src";

		#clock-cells = <1>;

drivers/clk/qcom/debugcc-sdmmagpie.c

+16 −96
Original line number Diff line number Diff line
@@ -83,15 +83,7 @@ static const char *const debug_mux_parent_names[] = { 
	"cam_cc_mclk1_clk",

	"cam_cc_mclk2_clk",

	"cam_cc_mclk3_clk",

	"cam_cc_qdss_debug_clk",

	"cam_cc_qdss_debug_xo_clk",

	"cam_cc_sleep_clk",

	"cam_cc_spdm_bps_clk",

	"cam_cc_spdm_ife_0_clk",

	"cam_cc_spdm_ife_0_csid_clk",

	"cam_cc_spdm_ipe_0_clk",

	"cam_cc_spdm_ipe_1_clk",

	"cam_cc_spdm_jpeg_clk",

	"disp_cc_mdss_ahb_clk",

	"disp_cc_mdss_byte0_clk",

	"disp_cc_mdss_byte0_intf_clk",
@@ -113,15 +105,7 @@ static const char *const debug_mux_parent_names[] = { 
	"disp_cc_mdss_rot_clk",

	"disp_cc_mdss_rscc_ahb_clk",

	"disp_cc_mdss_rscc_vsync_clk",

	"disp_cc_mdss_spdm_dp_crypto_clk",

	"disp_cc_mdss_spdm_dp_pixel1_clk",

	"disp_cc_mdss_spdm_dp_pixel_clk",

	"disp_cc_mdss_spdm_mdp_clk",

	"disp_cc_mdss_spdm_pclk0_clk",

	"disp_cc_mdss_spdm_pclk1_clk",

	"disp_cc_mdss_spdm_rot_clk",

	"disp_cc_mdss_vsync_clk",

	"disp_cc_sleep_clk",

	"disp_cc_xo_clk",

	"gcc_aggre_noc_pcie_tbu_clk",

	"gcc_aggre_ufs_phy_axi_clk",
@@ -155,13 +139,6 @@ static const char *const debug_mux_parent_names[] = { 
	"gcc_gpu_memnoc_gfx_clk",

	"gcc_gpu_snoc_dvm_gfx_clk",

	"gcc_gpu_vs_clk",

	"gcc_mss_axis2_clk",

	"gcc_mss_cfg_ahb_clk",

	"gcc_mss_gpll0_div_clk_src",

	"gcc_mss_mfab_axis_clk",

	"gcc_mss_q6_memnoc_axi_clk",

	"gcc_mss_snoc_axi_clk",

	"gcc_mss_vs_clk",

	"gcc_npu_axi_clk",

	"gcc_npu_cfg_ahb_clk",

	"gcc_npu_gpll0_clk_src",
@@ -235,6 +212,10 @@ static const char *const debug_mux_parent_names[] = { 
	"gcc_video_xo_clk",

	"gcc_vs_ctrl_ahb_clk",

	"gcc_vs_ctrl_clk",

	"measure_only_mccc_clk",

	"measure_only_cnoc_clk",

	"measure_only_ipa_2x_clk",

	"measure_only_snoc_clk",

	"gpu_cc_acd_ahb_clk",

	"gpu_cc_acd_cxo_clk",

	"gpu_cc_ahb_clk",
@@ -243,19 +224,13 @@ static const char *const debug_mux_parent_names[] = { 
	"gpu_cc_cx_gfx3d_clk",

	"gpu_cc_cx_gfx3d_slv_clk",

	"gpu_cc_cx_gmu_clk",

	"gpu_cc_cx_qdss_at_clk",

	"gpu_cc_cx_qdss_trig_clk",

	"gpu_cc_cx_qdss_tsctr_clk",

	"gpu_cc_cx_snoc_dvm_clk",

	"gpu_cc_cxo_aon_clk",

	"gpu_cc_cxo_clk",

	"gpu_cc_gx_cxo_clk",

	"gpu_cc_gx_gfx3d_clk",

	"gpu_cc_gx_gmu_clk",

	"gpu_cc_gx_qdss_tsctr_clk",

	"gpu_cc_gx_vsense_clk",

	"gpu_cc_sleep_clk",

	"gpu_cc_spdm_gx_gfx3d_div_clk",

	"npu_cc_armwic_core_clk",

	"npu_cc_bto_core_clk",

	"npu_cc_bwmon_clk",
@@ -282,9 +257,6 @@ static const char *const debug_mux_parent_names[] = { 
	"video_cc_mvs1_core_clk",

	"video_cc_mvsc_core_clk",

	"video_cc_mvsc_ctl_axi_clk",

	"video_cc_qdss_trig_clk",

	"video_cc_qdss_tsctr_div8_clk",

	"video_cc_sleep_clk",

	"video_cc_venus_ahb_clk",

	"video_cc_xo_clk",

	"l3_clk",
@@ -402,24 +374,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x3, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_mclk3_clk", 0x46, 4, CAM_CC,

			0x4, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_qdss_debug_clk", 0x46, 4, CAM_CC,

			0x3D, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_qdss_debug_xo_clk", 0x46, 4, CAM_CC,

			0x3E, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_sleep_clk", 0x46, 4, CAM_CC,

			0x3F, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_bps_clk", 0x46, 4, CAM_CC,

			0x2D, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_ife_0_clk", 0x46, 4, CAM_CC,

			0x31, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_ife_0_csid_clk", 0x46, 4, CAM_CC,

			0x32, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_ipe_0_clk", 0x46, 4, CAM_CC,

			0x2F, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_ipe_1_clk", 0x46, 4, CAM_CC,

			0x30, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "cam_cc_spdm_jpeg_clk", 0x46, 4, CAM_CC,

			0x34, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },

		{ "disp_cc_mdss_ahb_clk", 0x47, 4, DISP_CC,

			0x1F, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_byte0_clk", 0x47, 4, DISP_CC,
@@ -462,24 +418,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x22, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_rscc_vsync_clk", 0x47, 4, DISP_CC,

			0x21, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_dp_crypto_clk", 0x47, 4, DISP_CC,

			0x27, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_dp_pixel1_clk", 0x47, 4, DISP_CC,

			0x29, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_dp_pixel_clk", 0x47, 4, DISP_CC,

			0x28, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_mdp_clk", 0x47, 4, DISP_CC,

			0x25, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_pclk0_clk", 0x47, 4, DISP_CC,

			0x23, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_pclk1_clk", 0x47, 4, DISP_CC,

			0x24, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_spdm_rot_clk", 0x47, 4, DISP_CC,

			0x26, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_mdss_vsync_clk", 0x47, 4, DISP_CC,

			0x12, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_sleep_clk", 0x47, 4, DISP_CC,

			0x2B, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_xo_clk", 0x47, 4, DISP_CC,

			0x2A, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "gcc_aggre_noc_pcie_tbu_clk", 0x2D, 4, GCC,
@@ -546,20 +486,6 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x147, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_gpu_vs_clk", 0x112, 4, GCC,

			0x112, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_axis2_clk", 0x12F, 4, GCC,

			0x12F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_cfg_ahb_clk", 0x12D, 4, GCC,

			0x12D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_gpll0_div_clk_src", 0x133, 4, GCC,

			0x133, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_mfab_axis_clk", 0x12E, 4, GCC,

			0x12E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_q6_memnoc_axi_clk", 0x135, 4, GCC,

			0x135, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_snoc_axi_clk", 0x134, 4, GCC,

			0x134, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_mss_vs_clk", 0x111, 4, GCC,

			0x111, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_npu_axi_clk", 0x16A, 4, GCC,

			0x16A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_npu_cfg_ahb_clk", 0x169, 4, GCC,
@@ -706,6 +632,14 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x110, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gcc_vs_ctrl_clk", 0x10F, 4, GCC,

			0x10F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "measure_only_mccc_clk", 0xC2, 1, MC_CC,

			0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 },

		{ "measure_only_cnoc_clk", 0x15, 1, GCC,

			0x15, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 },

		{ "measure_only_ipa_2x_clk", 0x128, 1, GCC,

			0x128, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 },

		{ "measure_only_snoc_clk", 0x7, 1, GCC,

			0x7, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 },

		{ "gpu_cc_acd_ahb_clk", 0x144, 4, GPU_CC,

			0x20, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_acd_cxo_clk", 0x144, 4, GPU_CC,
@@ -722,12 +656,6 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x1B, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_gmu_clk", 0x144, 4, GPU_CC,

			0x19, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_at_clk", 0x144, 4, GPU_CC,

			0x13, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_trig_clk", 0x144, 4, GPU_CC,

			0x18, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_tsctr_clk", 0x144, 4, GPU_CC,

			0x14, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_snoc_dvm_clk", 0x144, 4, GPU_CC,

			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cxo_aon_clk", 0x144, 4, GPU_CC,
@@ -740,14 +668,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0xC, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_gmu_clk", 0x144, 4, GPU_CC,

			0x10, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_qdss_tsctr_clk", 0x144, 4, GPU_CC,

			0xE, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_vsense_clk", 0x144, 4, GPU_CC,

			0xD, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_sleep_clk", 0x144, 4, GPU_CC,

			0x17, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_spdm_gx_gfx3d_div_clk", 0x144, 4, GPU_CC,

			0x1E, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "npu_cc_armwic_core_clk", 0x16F, 4, NPU_CC,

			0x4, 0xFF, 0, 0x3, 0, 2, 0x4000, 0x3004, 0x3008 },

		{ "npu_cc_bto_core_clk", 0x16F, 4, NPU_CC,
@@ -800,12 +722,6 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x1, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_mvsc_ctl_axi_clk", 0x48, 4, VIDEO_CC,

			0xA, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_qdss_trig_clk", 0x48, 4, VIDEO_CC,

			0xD, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_qdss_tsctr_div8_clk", 0x48, 4, VIDEO_CC,

			0x10, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_sleep_clk", 0x48, 4, VIDEO_CC,

			0x9, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_venus_ahb_clk", 0x48, 4, VIDEO_CC,

			0xF, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 },

		{ "video_cc_xo_clk", 0x48, 4, VIDEO_CC,
@@ -905,6 +821,10 @@ static int clk_debug_sdmmagpie_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);

	if (ret)

		return ret;



	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);

	if (IS_ERR(clk)) {

		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");

drivers/clk/qcom/gcc-sdmmagpie.c

+4 −3
Original line number Diff line number Diff line
@@ -3009,14 +3009,15 @@ static struct clk_branch gcc_cpuss_gnoc_clk = { 
};



/* Measure-only clock for ddrss_gcc_debug_clk. */

static struct clk_dummy measure_only_bimc_clk = {

static struct clk_dummy measure_only_mccc_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_bimc_clk",

		.name = "measure_only_mccc_clk",

		.ops = &clk_dummy_ops,

	},

};





/* Measure-only clock for gcc_cfg_noc_ahb_clk. */

static struct clk_dummy measure_only_cnoc_clk = {

	.rrate = 1000,
@@ -3045,7 +3046,7 @@ static struct clk_dummy measure_only_snoc_clk = { 
};



struct clk_hw *gcc_sdmmagpie_hws[] = {

	[MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw,

	[MEASURE_ONLY_BIMC_CLK] = &measure_only_mccc_clk.hw,

	[MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw,

	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,

	[MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw,