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Commit dc8a9865 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ufs: snapshot of UFS driver & PHY driver"

parents dbd95d18 d89cd485

Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt

+4 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ Optional properties: 
                          with "phys" attribute, provides phandle to UFS PHY node

- vdd-hba-supply        : phandle to UFS host controller supply regulator node

- vcc-supply            : phandle to VCC supply regulator node

- vcc-voltage-level     : specifies voltage levels for VCC supply.

                          Should be specified in pairs (min, max), units uV.

- vccq-supply           : phandle to VCCQ supply regulator node

- vccq2-supply          : phandle to VCCQ2 supply regulator node

- vcc-supply-1p8        : For embedded UFS devices, valid VCC range is 1.7-1.95V
@@ -71,6 +73,8 @@ Optional properties: 
			  3: 52 MHz

			  Defaults to 26 MHz if not specified.

- extcon:       phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details).

- non-removable		: defines if the connected ufs device is not removable





Note: If above properties are not defined it can be assumed that the supply

regulators or clocks are always on.

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h

+15 −3
Original line number Diff line number Diff line
@@ -150,11 +150,15 @@ 
#define QSERDES_COM_CMN_VREG_SEL		COM_OFF(0x188)



/* UFS PHY TX registers */

#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX	TX_OFF(0, 0x44)

#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX	TX_OFF(0, 0x48)

#define QSERDES_TX0_TRANSCEIVER_BIAS_EN		TX_OFF(0, 0x5C)

#define QSERDES_TX0_LANE_MODE_1			TX_OFF(0, 0x8C)

#define QSERDES_TX0_LANE_MODE_2			TX_OFF(0, 0x90)

#define QSERDES_TX0_LANE_MODE_3			TX_OFF(0, 0x94)



#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX	TX_OFF(1, 0x44)

#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX	TX_OFF(1, 0x48)

#define QSERDES_TX1_LANE_MODE_1			TX_OFF(1, 0x8C)
@@ -177,6 +181,7 @@ 
#define QSERDES_RX0_SIGDET_LVL				RX_OFF(0, 0x108)

#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL		RX_OFF(0, 0x10C)

#define QSERDES_RX0_RX_INTERFACE_MODE			RX_OFF(0, 0x11C)

#define QSERDES_RX0_RX_MODE_00				RX_OFF(0, 0x164)



#define QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF		RX_OFF(1, 0x24)

#define QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER		RX_OFF(1, 0x28)
@@ -193,6 +198,7 @@ 
#define QSERDES_RX1_SIGDET_LVL				RX_OFF(1, 0x108)

#define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL		RX_OFF(1, 0x10C)

#define QSERDES_RX1_RX_INTERFACE_MODE			RX_OFF(1, 0x11C)

#define QSERDES_RX1_RX_MODE_00				RX_OFF(1, 0x164)



#define UFS_PHY_RX_LINECFG_DISABLE_BIT		BIT(1)
@@ -222,7 +228,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
@@ -254,13 +260,16 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00, 0x59),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6E),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -280,7 +289,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x5B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN, 0x04),
@@ -288,6 +297,9 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x81),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00, 0x59),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

drivers/scsi/ufs/ufs-debugfs.c

+9 −0
Original line number Diff line number Diff line
@@ -951,6 +951,10 @@ static int ufsdbg_show_hba_show(struct seq_file *file, void *data) 
	seq_printf(file, "hba->saved_err = 0x%x\n", hba->saved_err);

	seq_printf(file, "hba->saved_uic_err = 0x%x\n", hba->saved_uic_err);



	seq_printf(file, "power_mode_change_cnt = %d\n",

			hba->ufs_stats.power_mode_change_cnt);

	seq_printf(file, "hibern8_exit_cnt = %d\n",

			hba->ufs_stats.hibern8_exit_cnt);

	return 0;

}
@@ -1470,6 +1474,11 @@ void ufsdbg_set_err_state(struct ufs_hba *hba) 
	hba->debugfs_files.err_occurred = true;

}



void ufsdbg_clr_err_state(struct ufs_hba *hba)

{

	hba->debugfs_files.err_occurred = false;

}



DEFINE_SIMPLE_ATTRIBUTE(ufsdbg_err_state,

			ufsdbg_read_err_state,

			ufsdbg_clear_err_state,

drivers/scsi/ufs/ufs-debugfs.h

+4 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ void ufsdbg_remove_debugfs(struct ufs_hba *hba); 
void ufsdbg_pr_buf_to_std(struct ufs_hba *hba, int offset, int num_regs,

				char *str, void *priv);

void ufsdbg_set_err_state(struct ufs_hba *hba);

void ufsdbg_clr_err_state(struct ufs_hba *hba);

#else

static inline void ufsdbg_add_debugfs(struct ufs_hba *hba)

{
@@ -52,6 +53,9 @@ static inline void ufsdbg_pr_buf_to_std(struct ufs_hba *hba, int offset, 
void ufsdbg_set_err_state(struct ufs_hba *hba)

{

}

void ufsdbg_clr_err_state(struct ufs_hba *hba)

{

}

#endif



#ifdef CONFIG_UFS_FAULT_INJECTION

drivers/scsi/ufs/ufs-qcom-ice.c

+1 −1
Original line number Diff line number Diff line
@@ -394,8 +394,8 @@ int ufs_qcom_ice_cfg_start(struct ufs_qcom_host *qcom_host, 
	}





	if (qcom_host->ice.vops->config_start) {

	memset(&ice_set, 0, sizeof(ice_set));

	if (qcom_host->ice.vops->config_start) {



		spin_lock_irqsave(

			&qcom_host->ice_work_lock, flags);