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Commit dc03a047 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
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arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI 



Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.

Add their device tree nodes.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 2ea659a9

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -204,6 +204,28 @@ 
			#phy-cells = <1>;

		};



		ehci0: usb@01c1a000 {

			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";

			reg = <0x01c1a000 0x100>;

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_OHCI0>,

				 <&ccu CLK_BUS_EHCI0>,

				 <&ccu CLK_USB_OHCI0>;

			resets = <&ccu RST_BUS_OHCI0>,

				 <&ccu RST_BUS_EHCI0>;

			status = "disabled";

		};



		ohci0: usb@01c1a400 {

			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";

			reg = <0x01c1a400 0x100>;

			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_OHCI0>,

				 <&ccu CLK_USB_OHCI0>;

			resets = <&ccu RST_BUS_OHCI0>;

			status = "disabled";

		};



		ehci1: usb@01c1b000 {

			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";

			reg = <0x01c1b000 0x100>;