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Commit dbb02575 authored Jan 28, 2012 by Daniel Vetter

drm/i915: don't allow interlaced pipeconf on gen2



gen2 doesn't support it, so be a bit more paranoid and add a check to
ensure that we never ever set an unsupported interlaced bit.

Ensure that userspace can't set an interlaced mode by resetting
interlace_allowed for the crt on gen2. dvo and lvds are the only other
encoders that gen2 supports and these already disallow interlaced
modes.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 5def474e

drivers/gpu/drm/i915/intel_crt.c

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -594,6 +594,9 @@ void intel_crt_init(struct drm_device *dev)
	1 << INTEL_ANALOG_CLONE_BIT \|		1 << INTEL_ANALOG_CLONE_BIT \|
	1 << INTEL_SDVO_LVDS_CLONE_BIT);		1 << INTEL_SDVO_LVDS_CLONE_BIT);
	crt->base.crtc_mask = (1 << 0) \| (1 << 1);		crt->base.crtc_mask = (1 << 0) \| (1 << 1);
			if (IS_GEN2(dev))
			connector->interlace_allowed = 0;
			else
	connector->interlace_allowed = 1;		connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;		connector->doublescan_allowed = 0;

drivers/gpu/drm/i915/intel_display.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -5385,7 +5385,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
	}		}

	pipeconf &= ~PIPECONF_INTERLACE_MASK;		pipeconf &= ~PIPECONF_INTERLACE_MASK;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {		if (!IS_GEN2(dev) &&
			adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;		pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
	/* the chip adds 2 halflines automatically */		/* the chip adds 2 halflines automatically */
	adjusted_mode->crtc_vtotal -= 1;		adjusted_mode->crtc_vtotal -= 1;