Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit db695b5e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.1-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt 

Merge "ARM: mediatek: dts updates for v4.2" from Matthias Brugger:
- dts: add pinctrl/GPIO/EINT to mt8135
- dts: fix uart address for mt8127

* tag 'v4.1-next-dts' of https://github.com/mbgg/linux-mediatek:
  ARM: dts: mt8127: correct uart instance address
  ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135.
parents 0258b15d 7d580545

arch/arm/boot/dts/mt8127.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ 
			      <0 0x10216000 0 0x2000>;

		};



		uart0: serial@11006000 {

		uart0: serial@11002000 {

			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x400>;

			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
@@ -115,7 +115,7 @@ 
			status = "disabled";

		};



		uart1: serial@11007000 {

		uart1: serial@11003000 {

			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x400>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
@@ -123,7 +123,7 @@ 
			status = "disabled";

		};



		uart2: serial@11008000 {

		uart2: serial@11004000 {

			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x400>;

			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
@@ -131,7 +131,7 @@ 
			status = "disabled";

		};



		uart3: serial@11009000 {

		uart3: serial@11005000 {

			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";

			reg = <0 0x11005000 0 0x400>;

			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;

arch/arm/boot/dts/mt8135-pinfunc.h

0 → 100644
+1302 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/mt8135.dtsi

+29 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton64.dtsi"

#include "mt8135-pinfunc.h"



/ {

	compatible = "mediatek,mt8135";
@@ -101,6 +102,29 @@ 
		compatible = "simple-bus";

		ranges;



		/*

		 * Pinctrl access register at 0x10005000 and 0x1020c000 through

		 * regmap. Register 0x1000b000 is used by EINT.

		 */

		pio: pinctrl@10005000 {

			compatible = "mediatek,mt8135-pinctrl";

			reg = <0 0x1000b000 0 0x1000>;

			mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;

			pins-are-numbered;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

		};



		syscfg_pctl_a: syscfg_pctl_a@10005000 {

			compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";

			reg = <0 0x10005000 0 0x1000>;

		};



		timer: timer@10008000 {

			compatible = "mediatek,mt8135-timer",

					"mediatek,mt6577-timer";
@@ -119,6 +143,11 @@ 
			reg = <0 0x10200030 0 0x1c>;

		};



		syscfg_pctl_b: syscfg_pctl_b@1020c000 {

			compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";

			reg = <0 0x1020c000 0 0x1000>;

		};



		gic: interrupt-controller@10211000 {

			compatible = "arm,cortex-a15-gic";

			interrupt-controller;