Merge tag 'qcom-clocks-for-3.18' of... (db0bcc33) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/clk-pll.c

+67 −1

Original line number	Original line	Diff line number	Diff line
	@@ -97,7 +97,7 @@ static unsigned long
	clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)		clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	{		{
	struct clk_pll *pll = to_clk_pll(hw);		struct clk_pll *pll = to_clk_pll(hw);
	u32 l, m, n;		u32 l, m, n, config;
	unsigned long rate;		unsigned long rate;
	u64 tmp;		u64 tmp;

	@@ -116,13 +116,79 @@ clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	do_div(tmp, n);		do_div(tmp, n);
	rate += tmp;		rate += tmp;
	}		}
			if (pll->post_div_width) {
			regmap_read(pll->clkr.regmap, pll->config_reg, &config);
			config >>= pll->post_div_shift;
			config &= BIT(pll->post_div_width) - 1;
			rate /= config + 1;
			}

	return rate;		return rate;
	}		}

			static const
			struct pll_freq_tbl find_freq(const struct pll_freq_tbl f, unsigned long rate)
			{
			if (!f)
			return NULL;

			for (; f->freq; f++)
			if (rate <= f->freq)
			return f;

			return NULL;
			}

			static long
			clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
			unsigned long p_rate, struct clk *p)
			{
			struct clk_pll *pll = to_clk_pll(hw);
			const struct pll_freq_tbl *f;

			f = find_freq(pll->freq_tbl, rate);
			if (!f)
			return clk_pll_recalc_rate(hw, *p_rate);

			return f->freq;
			}

			static int
			clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
			{
			struct clk_pll *pll = to_clk_pll(hw);
			const struct pll_freq_tbl *f;
			bool enabled;
			u32 mode;
			u32 enable_mask = PLL_OUTCTRL \| PLL_BYPASSNL \| PLL_RESET_N;

			f = find_freq(pll->freq_tbl, rate);
			if (!f)
			return -EINVAL;

			regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
			enabled = (mode & enable_mask) == enable_mask;

			if (enabled)
			clk_pll_disable(hw);

			regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
			regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
			regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
			regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);

			if (enabled)
			clk_pll_enable(hw);

			return 0;
			}

	const struct clk_ops clk_pll_ops = {		const struct clk_ops clk_pll_ops = {
	.enable = clk_pll_enable,		.enable = clk_pll_enable,
	.disable = clk_pll_disable,		.disable = clk_pll_disable,
	.recalc_rate = clk_pll_recalc_rate,		.recalc_rate = clk_pll_recalc_rate,
			.determine_rate = clk_pll_determine_rate,
			.set_rate = clk_pll_set_rate,
	};		};
	EXPORT_SYMBOL_GPL(clk_pll_ops);		EXPORT_SYMBOL_GPL(clk_pll_ops);

drivers/clk/qcom/clk-pll.h

+20 −0

Original line number	Original line	Diff line number	Diff line
	@@ -17,6 +17,21 @@
	#include <linux/clk-provider.h>		#include <linux/clk-provider.h>
	#include "clk-regmap.h"		#include "clk-regmap.h"

			/**
			* struct pll_freq_tbl - PLL frequency table
			* @l: L value
			* @m: M value
			* @n: N value
			* @ibits: internal values
			*/
			struct pll_freq_tbl {
			unsigned long freq;
			u16 l;
			u16 m;
			u16 n;
			u32 ibits;
			};

	/**		/**
	* struct clk_pll - phase locked loop (PLL)		* struct clk_pll - phase locked loop (PLL)
	* @l_reg: L register		* @l_reg: L register
	@@ -26,6 +41,7 @@
	* @mode_reg: mode register		* @mode_reg: mode register
	* @status_reg: status register		* @status_reg: status register
	* @status_bit: ANDed with @status_reg to determine if PLL is enabled		* @status_bit: ANDed with @status_reg to determine if PLL is enabled
			* @freq_tbl: PLL frequency table
	* @hw: handle between common and hardware-specific interfaces		* @hw: handle between common and hardware-specific interfaces
	*/		*/
	struct clk_pll {		struct clk_pll {
	@@ -36,6 +52,10 @@ struct clk_pll {
	u32 mode_reg;		u32 mode_reg;
	u32 status_reg;		u32 status_reg;
	u8 status_bit;		u8 status_bit;
			u8 post_div_width;
			u8 post_div_shift;

			const struct pll_freq_tbl *freq_tbl;

	struct clk_regmap clkr;		struct clk_regmap clkr;
	};		};

drivers/clk/qcom/clk-rcg.c

+54 −61

Original line number	Original line	Diff line number	Diff line
	@@ -21,6 +21,7 @@
	#include <asm/div64.h>		#include <asm/div64.h>

	#include "clk-rcg.h"		#include "clk-rcg.h"
			#include "common.h"

	static u32 ns_to_src(struct src_sel *s, u32 ns)		static u32 ns_to_src(struct src_sel *s, u32 ns)
	{		{
	@@ -67,16 +68,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
	{		{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);		struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	int num_parents = __clk_get_num_parents(hw->clk);		int num_parents = __clk_get_num_parents(hw->clk);
	u32 ns, ctl;		u32 ns, reg;
	int bank;		int bank;
	int i;		int i;
	struct src_sel *s;		struct src_sel *s;

	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	bank = reg_to_bank(rcg, ctl);		bank = reg_to_bank(rcg, reg);
	s = &rcg->s[bank];		s = &rcg->s[bank];

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);		regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
	ns = ns_to_src(s, ns);		ns = ns_to_src(s, ns);

	for (i = 0; i < num_parents; i++)		for (i = 0; i < num_parents; i++)
	@@ -192,90 +193,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)

	static void configure_bank(struct clk_dyn_rcg rcg, const struct freq_tbl f)		static void configure_bank(struct clk_dyn_rcg rcg, const struct freq_tbl f)
	{		{
	u32 ns, md, ctl, *regp;		u32 ns, md, reg;
	int bank, new_bank;		int bank, new_bank;
	struct mn *mn;		struct mn *mn;
	struct pre_div *p;		struct pre_div *p;
	struct src_sel *s;		struct src_sel *s;
	bool enabled;		bool enabled;
	u32 md_reg;		u32 md_reg, ns_reg;
	u32 bank_reg;
	bool banked_mn = !!rcg->mn[1].width;		bool banked_mn = !!rcg->mn[1].width;
			bool banked_p = !!rcg->p[1].pre_div_width;
	struct clk_hw *hw = &rcg->clkr.hw;		struct clk_hw *hw = &rcg->clkr.hw;

	enabled = __clk_is_enabled(hw->clk);		enabled = __clk_is_enabled(hw->clk);

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);		bank = reg_to_bank(rcg, reg);

	if (banked_mn) {
	regp = &ctl;
	bank_reg = rcg->clkr.enable_reg;
	} else {
	regp = &ns;
	bank_reg = rcg->ns_reg;
	}

	bank = reg_to_bank(rcg, *regp);
	new_bank = enabled ? !bank : bank;		new_bank = enabled ? !bank : bank;

			ns_reg = rcg->ns_reg[new_bank];
			regmap_read(rcg->clkr.regmap, ns_reg, &ns);

	if (banked_mn) {		if (banked_mn) {
	mn = &rcg->mn[new_bank];		mn = &rcg->mn[new_bank];
	md_reg = rcg->md_reg[new_bank];		md_reg = rcg->md_reg[new_bank];

	ns \|= BIT(mn->mnctr_reset_bit);		ns \|= BIT(mn->mnctr_reset_bit);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);		regmap_write(rcg->clkr.regmap, ns_reg, ns);

	regmap_read(rcg->clkr.regmap, md_reg, &md);		regmap_read(rcg->clkr.regmap, md_reg, &md);
	md = mn_to_md(mn, f->m, f->n, md);		md = mn_to_md(mn, f->m, f->n, md);
	regmap_write(rcg->clkr.regmap, md_reg, md);		regmap_write(rcg->clkr.regmap, md_reg, md);

	ns = mn_to_ns(mn, f->m, f->n, ns);		ns = mn_to_ns(mn, f->m, f->n, ns);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);		regmap_write(rcg->clkr.regmap, ns_reg, ns);

	ctl = mn_to_reg(mn, f->m, f->n, ctl);		/* Two NS registers means mode control is in NS register */
	regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);		if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
			ns = mn_to_reg(mn, f->m, f->n, ns);
			regmap_write(rcg->clkr.regmap, ns_reg, ns);
			} else {
			reg = mn_to_reg(mn, f->m, f->n, reg);
			regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
			}

	ns &= ~BIT(mn->mnctr_reset_bit);		ns &= ~BIT(mn->mnctr_reset_bit);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);		regmap_write(rcg->clkr.regmap, ns_reg, ns);
	} else {		}

			if (banked_p) {
	p = &rcg->p[new_bank];		p = &rcg->p[new_bank];
	ns = pre_div_to_ns(p, f->pre_div - 1, ns);		ns = pre_div_to_ns(p, f->pre_div - 1, ns);
	}		}

	s = &rcg->s[new_bank];		s = &rcg->s[new_bank];
	ns = src_to_ns(s, s->parent_map[f->src], ns);		ns = src_to_ns(s, s->parent_map[f->src], ns);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);		regmap_write(rcg->clkr.regmap, ns_reg, ns);

	if (enabled) {		if (enabled) {
	*regp ^= BIT(rcg->mux_sel_bit);		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	regmap_write(rcg->clkr.regmap, bank_reg, *regp);		reg ^= BIT(rcg->mux_sel_bit);
			regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
	}		}
	}		}

	static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)		static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
	{		{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);		struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	u32 ns, ctl, md, reg;		u32 ns, md, reg;
	int bank;		int bank;
	struct freq_tbl f = { 0 };		struct freq_tbl f = { 0 };
	bool banked_mn = !!rcg->mn[1].width;		bool banked_mn = !!rcg->mn[1].width;
			bool banked_p = !!rcg->p[1].pre_div_width;

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
	reg = banked_mn ? ctl : ns;

	bank = reg_to_bank(rcg, reg);		bank = reg_to_bank(rcg, reg);

			regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

	if (banked_mn) {		if (banked_mn) {
	regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
	f.m = md_to_m(&rcg->mn[bank], md);		f.m = md_to_m(&rcg->mn[bank], md);
	f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
	} else {
	f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
	}		}
	f.src = index;

			if (banked_p)
			f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;

			f.src = index;
	configure_bank(rcg, &f);		configure_bank(rcg, &f);

	return 0;		return 0;
	@@ -336,41 +340,30 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	u32 m, n, pre_div, ns, md, mode, reg;		u32 m, n, pre_div, ns, md, mode, reg;
	int bank;		int bank;
	struct mn *mn;		struct mn *mn;
			bool banked_p = !!rcg->p[1].pre_div_width;
	bool banked_mn = !!rcg->mn[1].width;		bool banked_mn = !!rcg->mn[1].width;

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);

	if (banked_mn)
	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &reg);
	else
	reg = ns;

	bank = reg_to_bank(rcg, reg);		bank = reg_to_bank(rcg, reg);

			regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
			m = n = pre_div = mode = 0;

	if (banked_mn) {		if (banked_mn) {
	mn = &rcg->mn[bank];		mn = &rcg->mn[bank];
	regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
	m = md_to_m(mn, md);		m = md_to_m(mn, md);
	n = ns_m_to_n(mn, ns, m);		n = ns_m_to_n(mn, ns, m);
			/* Two NS registers means mode control is in NS register */
			if (rcg->ns_reg[0] != rcg->ns_reg[1])
			reg = ns;
	mode = reg_to_mnctr_mode(mn, reg);		mode = reg_to_mnctr_mode(mn, reg);
	return calc_rate(parent_rate, m, n, mode, 0);
	} else {
	pre_div = ns_to_pre_div(&rcg->p[bank], ns);
	return calc_rate(parent_rate, 0, 0, 0, pre_div);
	}		}
	}

	static const
	struct freq_tbl find_freq(const struct freq_tbl f, unsigned long rate)
	{
	if (!f)
	return NULL;

	for (; f->freq; f++)		if (banked_p)
	if (rate <= f->freq)		pre_div = ns_to_pre_div(&rcg->p[bank], ns);
	return f;

	return NULL;		return calc_rate(parent_rate, m, n, mode, pre_div);
	}		}

	static long _freq_tbl_determine_rate(struct clk_hw *hw,		static long _freq_tbl_determine_rate(struct clk_hw *hw,
	@@ -379,7 +372,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
	{		{
	unsigned long clk_flags;		unsigned long clk_flags;

	f = find_freq(f, rate);		f = qcom_find_freq(f, rate);
	if (!f)		if (!f)
	return -EINVAL;		return -EINVAL;

	@@ -477,7 +470,7 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
	struct clk_rcg *rcg = to_clk_rcg(hw);		struct clk_rcg *rcg = to_clk_rcg(hw);
	const struct freq_tbl *f;		const struct freq_tbl *f;

	f = find_freq(rcg->freq_tbl, rate);		f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)		if (!f)
	return -EINVAL;		return -EINVAL;

	@@ -497,7 +490,7 @@ static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);		struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	const struct freq_tbl *f;		const struct freq_tbl *f;

	f = find_freq(rcg->freq_tbl, rate);		f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)		if (!f)
	return -EINVAL;		return -EINVAL;

drivers/clk/qcom/clk-rcg.h

+4 −2

Original line number	Original line	Diff line number	Diff line
	@@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
	* struct clk_dyn_rcg - root clock generator with glitch free mux		* struct clk_dyn_rcg - root clock generator with glitch free mux
	*		*
	* @mux_sel_bit: bit to switch glitch free mux		* @mux_sel_bit: bit to switch glitch free mux
	* @ns_reg: NS register		* @ns_reg: NS0 and NS1 register
	* @md_reg: MD0 and MD1 register		* @md_reg: MD0 and MD1 register
			* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
	* @mn: mn counter (banked)		* @mn: mn counter (banked)
	* @s: source selector (banked)		* @s: source selector (banked)
	* @freq_tbl: frequency table		* @freq_tbl: frequency table
	@@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
	*		*
	*/		*/
	struct clk_dyn_rcg {		struct clk_dyn_rcg {
	u32 ns_reg;		u32 ns_reg[2];
	u32 md_reg[2];		u32 md_reg[2];
			u32 bank_reg;

	u8 mux_sel_bit;		u8 mux_sel_bit;

drivers/clk/qcom/clk-rcg2.c

+3 −16

Original line number	Original line	Diff line number	Diff line
	@@ -24,6 +24,7 @@
	#include <asm/div64.h>		#include <asm/div64.h>

	#include "clk-rcg.h"		#include "clk-rcg.h"
			#include "common.h"

	#define CMD_REG 0x0		#define CMD_REG 0x0
	#define CMD_UPDATE BIT(0)		#define CMD_UPDATE BIT(0)
	@@ -172,27 +173,13 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	return calc_rate(parent_rate, m, n, mode, hid_div);		return calc_rate(parent_rate, m, n, mode, hid_div);
	}		}

	static const
	struct freq_tbl find_freq(const struct freq_tbl f, unsigned long rate)
	{
	if (!f)
	return NULL;

	for (; f->freq; f++)
	if (rate <= f->freq)
	return f;

	/* Default to our fastest rate */
	return f - 1;
	}

	static long _freq_tbl_determine_rate(struct clk_hw *hw,		static long _freq_tbl_determine_rate(struct clk_hw *hw,
	const struct freq_tbl *f, unsigned long rate,		const struct freq_tbl *f, unsigned long rate,
	unsigned long p_rate, struct clk *p)		unsigned long p_rate, struct clk *p)
	{		{
	unsigned long clk_flags;		unsigned long clk_flags;

	f = find_freq(f, rate);		f = qcom_find_freq(f, rate);
	if (!f)		if (!f)
	return -EINVAL;		return -EINVAL;

	@@ -268,7 +255,7 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
	struct clk_rcg2 *rcg = to_clk_rcg2(hw);		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
	const struct freq_tbl *f;		const struct freq_tbl *f;

	f = find_freq(rcg->freq_tbl, rate);		f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)		if (!f)
	return -EINVAL;		return -EINVAL;