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Commit daee0e4f authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add UFS support for sm6150 mtp platform"

parents e6d81ae6 7992f5a4

Documentation/devicetree/bindings/ufs/ufs-qcom.txt

+4 −1
Original line number Diff line number Diff line
@@ -18,7 +18,10 @@ Required properties: 
		        "qcom,ufs-phy-qmp-v3-falcon" for phy support

			 for msmfalcon

			"qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy

			 present on MSM8996 chipset.

			 present on MSM8996 chipset

			"qcom,ufs-phy-qmp-v3-660" for V3 phy support on

			 sm6150 platform



- reg               : should contain PHY register address space (mandatory),

- reg-names         : indicates various resources passed to driver (via reg proptery) by name.

                      Required "reg-names" is "phy_mem".

arch/arm64/boot/dts/qcom/sm6150-cdp.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -31,3 +31,31 @@ 
&pm6150l_lcdb {

	status = "ok";

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v3-660";



	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */

	vdda-pll-supply = <&pm6150_l11>;

	vdda-phy-max-microamp = <30000>;

	vdda-pll-max-microamp = <12000>;



	status = "ok";

};



&ufshc_mem {

	vdd-hba-supply = <&ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm6150l_l11>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm6150_l12>;

	vcc-max-microamp = <600000>;

	vccq2-max-microamp = <600000>;



	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;

	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vddp-ref-clk-min-uV = <1232000>;

	qcom,vddp-ref-clk-max-uV = <1260000>;



	status = "ok";

};

arch/arm64/boot/dts/qcom/sm6150-mtp.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -27,3 +27,31 @@ 
&pm6150l_lcdb {

	status = "ok";

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v3-660";



	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */

	vdda-pll-supply = <&pm6150_l11>;

	vdda-phy-max-microamp = <30000>;

	vdda-pll-max-microamp = <12000>;



	status = "ok";

};



&ufshc_mem {

	vdd-hba-supply = <&ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm6150l_l11>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm6150_l12>;

	vcc-max-microamp = <600000>;

	vccq2-max-microamp = <600000>;



	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;

	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vddp-ref-clk-min-uV = <1232000>;

	qcom,vddp-ref-clk-max-uV = <1260000>;



	status = "ok";

};

arch/arm64/boot/dts/qcom/sm6150-qrd.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -14,3 +14,31 @@ 


&soc {

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v3-660";



	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */

	vdda-pll-supply = <&pm6150_l11>;

	vdda-phy-max-microamp = <30000>;

	vdda-pll-max-microamp = <12000>;



	status = "ok";

};



&ufshc_mem {

	vdd-hba-supply = <&ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm6150l_l11>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm6150_l12>;

	vcc-max-microamp = <600000>;

	vccq2-max-microamp = <600000>;



	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;

	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vddp-ref-clk-min-uV = <1232000>;

	qcom,vddp-ref-clk-max-uV = <1260000>;



	status = "ok";

};

arch/arm64/boot/dts/qcom/sm6150.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,39 @@ 
			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <12>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<123 512 0 0>, <1 757 0 0>,          /* No vote */

		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x3f 0xC0>;

		qcom,pm-qos-cpu-group-latency-us = <67 67>;