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Commit dad03f4a authored by Jack Pham's avatar Jack Pham
Browse files

ARM: dts: msm: Add macros for QMP USB register offsets on SDM855 



Add macro definitions in a dt-bindings header file for all
the QMP USB DP and USB UNI PHY register offsets. This allows
for more straightforward entry in the DTS and aims to help
reduce typographical errors.

Change-Id: I61d2fab3e98c47fcb3d4a83a204584063d6db2f9
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent a6100e9d

arch/arm64/boot/dts/qcom/sdm855-usb.dtsi

+137 −136
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include <dt-bindings/clock/qcom,gcc-sdm855.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/phy/qcom,sdm855-qmp-usb3.h>



&soc {

	/* Primary USB port related controller */
@@ -144,144 +145,144 @@ 
		qcom,vbus-valid-override;

		qcom,qmp-phy-init-seq =

		    /* <reg_offset, value, delay> */

			<0x1010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */

			 0x101c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */

			 0x1020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */

			 0x1024 0xde 0x00 /* QSERDES_COM_SSC_STEP_SIZE1_MODE0 */

			 0x1028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2_MODE0 */

			 0x1030 0xde 0x00 /* QSERDES_COM_SSC_STEP_SIZE1_MODE1 */

			 0x1034 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2_MODE1 */

			 0x1050 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */

			 0x1074 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */

			 0x1078 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE1 */

			 0x107c 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */

			 0x1080 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE1 */

			 0x1084 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */

			 0x1088 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE1 */

			 0x1094 0x1a 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */

			 0x10a4 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */

			 0x10ac 0x14 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */

			 0x10b0 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */

			 0x10b4 0x34 0x00 /* QSERDES_COM_LOCK_CMP1_MODE1 */

			 0x10b8 0x82 0x00 /* QSERDES_COM_LOCK_CMP2_MODE1 */

			 0x10bc 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */

			 0x10c4 0x82 0x00 /* QSERDES_COM_DEC_START_MODE1 */

			 0x10cc 0xab 0x00 /* COM_DIV_FRAC_START1_MODE0 */

			 0x10d0 0xea 0x00 /* COM_DIV_FRAC_START2_MODE0 */

			 0x10d4 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */

			 0x10d8 0xab 0x00 /* COM_DIV_FRAC_START1_MODE1 */

			 0x10dc 0xea 0x00 /* COM_DIV_FRAC_START2_MODE1 */

			 0x10e0 0x02 0x00 /* COM_DIV_FRAC_START3_MODE1 */

			 0x1108 0x00 0x00 /* QSERDES_COM_VCO_TUNE_CTRL */

			 0x110c 0x02 0x00 /* QSERDES_COM_VCO_TUNE_MAP */

			 0x1110 0x24 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */

			 0x1118 0x24 0x00 /* QSERDES_COM_VCO_TUNE1_MODE1 */

			 0x111c 0x02 0x00 /* QSERDES_COM_VCO_TUNE2_MODE1 */

			 0x1158 0x01 0x00 /* QSERDES_COM_HSCLK_SEL */

			 0x116c 0x08 0x00 /* QSERDES_COM_CORECLK_DIV_MODE1 */

			 0x11ac 0xca 0x00 /* COM_BIN_VCOCAL_CMP_CODE1_MODE0 */

			 0x11b0 0x1e 0x00 /* COM_BIN_VCOCAL_CMP_CODE2_MODE0 */

			 0x11b4 0xca 0x00 /* COM_BIN_VCOCAL_CMP_CODE1_MODE1 */

			 0x11b8 0x1e 0x00 /* COM_BIN_VCOCAL_CMP_CODE2_MODE1 */

			 0x11bc 0x11 0x00 /* QSERDES_COM_BIN_VCOCAL_HSCLK_SEL */

			 0x1284 0x05 0x00 /* QSERDES_TXA_LANE_MODE_1 */

			 0x129c 0x12 0x00 /* QSERDES_TXA_RCV_DETECT_LVL_2 */

			 0x1414 0x04 0x00 /* QSERDES_RXA_UCDR_SO_GAIN */

			 0x1430 0x2f 0x00 /* RXA_UCDR_FASTLOCK_FO_GAIN */

			 0x1434 0x7f 0x00 /* RXA_UCDR_SO_SATURATION_AND_ENABL */

			 0x143c 0xff 0x00 /* RXA_UCDR_FASTLOCK_COUNT_LOW */

			 0x1440 0x0f 0x00 /* RXA_UCDR_FASTLOCK_COUNT_HIGH */

			 0x1444 0x99 0x00 /* QSERDES_RXA_UCDR_PI_CONTROLS */

			 0x144c 0x04 0x00 /* QSERDES_RXA_UCDR_SB2_THRESH1 */

			 0x1450 0x08 0x00 /* QSERDES_RXA_UCDR_SB2_THRESH2 */

			 0x1454 0x05 0x00 /* QSERDES_RXA_UCDR_SB2_GAIN1 */

			 0x1458 0x05 0x00 /* QSERDES_RXA_UCDR_SB2_GAIN2 */

			 0x14d8 0x03 0x00 /* QSERDES_RXA_VGA_CAL_CNTRL2 */

			 0x14ec 0x0f 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL2 */

			 0x14f0 0x4a 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL3 */

			 0x14f4 0x08 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL4 */

			 0x14f8 0xc0 0x00 /* RXA_RX_IDAC_TSETTLE_LOW */

			 0x14fc 0x00 0x00 /* QSERDES_RXA_RX_IDAC_TSETTLE_HIGH */

			 0x1510 0x77 0x00 /* RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */

			 0x1514 0x80 0x00 /* RXA_RX_OFFSET_ADAPTOR_CNTRL2 */

			 0x151c 0x04 0x00 /* QSERDES_RXA_SIGDET_CNTRL */

			 0x1524 0x0e 0x00 /* RXA_SIGDET_DEGLITCH_CNTRL */

			 0x1570 0x36 0x00 /* QSERDES_RXA_RX_MODE_00_LOW */

			 0x1574 0x36 0x00 /* QSERDES_RXA_RX_MODE_00_HIGH */

			 0x1578 0xb6 0x00 /* QSERDES_RXA_RX_MODE_00_HIGH2 */

			 0x157c 0x17 0x00 /* QSERDES_RXA_RX_MODE_00_HIGH3 */

			 0x1580 0x7c 0x00 /* QSERDES_RXA_RX_MODE_00_HIGH4 */

			 0x1584 0xd4 0x00 /* QSERDES_RXA_RX_MODE_01_LOW */

			 0x1588 0x54 0x00 /* QSERDES_RXA_RX_MODE_01_HIGH */

			 0x158c 0xdb 0x00 /* QSERDES_RXA_RX_MODE_01_HIGH2 */

			 0x1590 0x39 0x00 /* QSERDES_RXA_RX_MODE_01_HIGH3 */

			 0x1594 0x31 0x00 /* QSERDES_RXA_RX_MODE_01_HIGH4 */

			 0x15b4 0x04 0x00 /* QSERDES_RXA_DFE_EN_TIMER */

			 0x15b8 0x30 0x00 /* RXA_DFE_CTLE_POST_CAL_OFFSET */

			 0x1684 0x05 0x00 /* QSERDES_TXB_LANE_MODE_1 */

			 0x169c 0x12 0x00 /* QSERDES_TXB_RCV_DETECT_LVL_2 */

			 0x1814 0x04 0x00 /* QSERDES_RXB_UCDR_SO_GAIN */

			 0x1830 0x2f 0x00 /* RXB_UCDR_FASTLOCK_FO_GAIN */

			 0x1834 0x7f 0x00 /* RXB_UCDR_SO_SATURATION_AND_ENABL */

			 0x183c 0xff 0x00 /* RXB_UCDR_FASTLOCK_COUNT_LOW */

			 0x1840 0x0f 0x00 /* RXB_UCDR_FASTLOCK_COUNT_HIGH */

			 0x1844 0x99 0x00 /* QSERDES_RXB_UCDR_PI_CONTROLS */

			 0x184c 0x04 0x00 /* QSERDES_RXB_UCDR_SB2_THRESH1 */

			 0x1850 0x08 0x00 /* QSERDES_RXB_UCDR_SB2_THRESH2 */

			 0x1854 0x05 0x00 /* QSERDES_RXB_UCDR_SB2_GAIN1 */

			 0x1858 0x05 0x00 /* QSERDES_RXB_UCDR_SB2_GAIN2 */

			 0x18d8 0x03 0x00 /* QSERDES_RXB_VGA_CAL_CNTRL2 */

			 0x18ec 0x0f 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL2 */

			 0x18f0 0x4a 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL3 */

			 0x18f4 0x08 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL4 */

			 0x18f8 0xc0 0x00 /* QSERDES_RXB_RX_IDAC_TSETTLE_LOW */

			 0x18fc 0x00 0x00 /* RXB_RX_IDAC_TSETTLE_HIGH */

			 0x1910 0x77 0x00 /* RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */

			 0x1914 0x80 0x00 /* RXB_RX_OFFSET_ADAPTOR_CNTRL2 */

			 0x191c 0x04 0x00 /* QSERDES_RXB_SIGDET_CNTRL */

			 0x1924 0x0e 0x00 /* RXB_SIGDET_DEGLITCH_CNTRL */

			 0x1970 0x36 0x00 /* QSERDES_RXB_RX_MODE_00_LOW */

			 0x1974 0x36 0x00 /* QSERDES_RXB_RX_MODE_00_HIGH */

			 0x1978 0xb6 0x00 /* QSERDES_RXB_RX_MODE_00_HIGH2 */

			 0x197c 0x17 0x00 /* QSERDES_RXB_RX_MODE_00_HIGH3 */

			 0x1980 0x7c 0x00 /* QSERDES_RXB_RX_MODE_00_HIGH4 */

			 0x1984 0xd4 0x00 /* QSERDES_RXB_RX_MODE_01_LOW */

			 0x1988 0x54 0x00 /* QSERDES_RXB_RX_MODE_01_HIGH */

			 0x198c 0xdb 0x00 /* QSERDES_RXB_RX_MODE_01_HIGH2 */

			 0x1990 0x39 0x00 /* QSERDES_RXB_RX_MODE_01_HIGH3 */

			 0x1994 0x31 0x00 /* QSERDES_RXB_RX_MODE_01_HIGH4 */

			 0x19b4 0x04 0x00 /* QSERDES_RXB_DFE_EN_TIMER */

			 0x19b8 0x30 0x00 /* RXB_DFE_CTLE_POST_CAL_OFFSET */

			 0x1cc4 0xd0 0x00 /* PCS_LOCK_DETECT_CONFIG1 */

			 0x1cc8 0x17 0x00 /* PCS_LOCK_DETECT_CONFIG2 */

			 0x1ccc 0x20 0x00 /* PCS_LOCK_DETECT_CONFIG3 */

			 0x1d88 0x88 0x00 /* PCS_RX_SIGDET_LVL */

			 0x1dc0 0x88 0x00 /* PCS_ALIGN_DETECT_CONFIG1 */

			 0x1dc4 0x13 0x00 /* PCS_ALIGN_DETECT_CONFIG2 */

			 0x1ddc 0x0d 0x00 /* PCS_EQ_CONFIG1 */

			 0x1f18 0x64 0x00 /* PCS_USB3_LFPS_DET_HIGH_COUNT_VAL */

			 0x1f28 0x55 0x00 /* PCS_USB3_RXEQTRAINING_LOCK_TIME */

			 0x1f2c 0x30 0x00 /* PCS_USB3_RXEQTRAINING_WAIT_TIME */

			 0x1f30 0x05 0x00 /* PCS_USB3_RXEQTRAINING_CTLE_TIME */

			 0x1f34 0x15 0x00 /* USB3_RXEQTRAINING_WAIT_TIME_S2 */

			 0x1f38 0x04 0x00 /* USB3_RXEQTRAINING_DFE_TIME_S2 */

		    <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0

		     USB3_DP_QSERDES_COM_SSC_PER1 0x31 0

		     USB3_DP_QSERDES_COM_SSC_PER2 0x01 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

		     USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

		     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

		     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

		     USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

		     USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

		     USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0

		     USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0

		     USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

		     USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

		     USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

		     USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

		     USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0

		     USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

		     USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x00 0

		     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

		     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

		     USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

		     USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

		     USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

		     USB3_DP_QSERDES_TXA_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0

		     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2f 0

		     USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

		     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xff 0

		     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

		     USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x08 0

		     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

		     USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

		     USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x36 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x36 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xd4 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x54 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xdb 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x39 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x31 0

		     USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_QSERDES_TXB_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0

		     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2f 0

		     USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

		     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xff 0

		     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

		     USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x08 0

		     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

		     USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

		     USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x36 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x36 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xd4 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x54 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xdb 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x39 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x31 0

		     USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x17 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_DP_PCS_RX_SIGDET_LVL 0x88 0

		     USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

		     USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_DP_PCS_EQ_CONFIG1 0x0d 0

		     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x64 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x55 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x05 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x15 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x04 0

		     0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

			<0x1c14 /* USB3_DP_PCS_PCS_STATUS1 */

			 0x1f08 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */

			 0x1f14 /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */

			 0x1c40 /* USB3_DP_PCS_POWER_DOWN_CONTROL */

			 0x1c00 /* USB3_DP_PCS_SW_RESET */

			 0x1c44 /* USB3_DP_PCS_START_CONTROL */

			<USB3_DP_PCS_PCS_STATUS1

			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL

			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR

			 USB3_DP_PCS_POWER_DOWN_CONTROL

			 USB3_DP_PCS_SW_RESET

			 USB3_DP_PCS_START_CONTROL

			 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */

			 0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */

			 0x0004 /* USB3_DP_COM_SW_RESET */

			 0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */

			 0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */

			 0x0010 /* USB3_DP_COM_TYPEC_CTRL */

			 0x000c /* USB3_DP_COM_SWI_CTRL */

			 0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */

			 USB3_DP_COM_POWER_DOWN_CTRL

			 USB3_DP_COM_SW_RESET

			 USB3_DP_COM_RESET_OVRD_CTRL

			 USB3_DP_COM_PHY_MODE_CTRL

			 USB3_DP_COM_TYPEC_CTRL

			 USB3_DP_COM_SWI_CTRL

			 USB3_DP_PCS_MISC_CLAMP_ENABLE>;



		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

include/dt-bindings/phy/qcom,sdm855-qmp-usb3.h

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