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Commit dab75dd9 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: Simplify ptrace_getfpregs FPU IR retrieval 



All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6147/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3351047f

arch/mips/kernel/ptrace.c

+1 −24
Original line number Diff line number Diff line
@@ -114,7 +114,6 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data) 
int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)

{

	int i;

	unsigned int tmp;



	if (!access_ok(VERIFY_WRITE, data, 33 * 8))

		return -EIO;
@@ -130,29 +129,7 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) 
	}



	__put_user(child->thread.fpu.fcr31, data + 64);



	preempt_disable();

	if (cpu_has_fpu) {

		unsigned int flags;



		if (cpu_has_mipsmt) {

			unsigned int vpflags = dvpe();

			flags = read_c0_status();

			__enable_fpu(FPU_AS_IS);

			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));

			write_c0_status(flags);

			evpe(vpflags);

		} else {

			flags = read_c0_status();

			__enable_fpu(FPU_AS_IS);

			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));

			write_c0_status(flags);

		}

	} else {

		tmp = 0;

	}

	preempt_enable();

	__put_user(tmp, data + 65);

	__put_user(current_cpu_data.fpu_id, data + 65);



	return 0;

}