Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d9ac0e5b authored by Charan Teja Reddy's avatar Charan Teja Reddy Committed by Prakash Gupta
Browse files

iommu: arm-smmu: clear sid in DEBUG_SID_HALT_REG during ecats 



Clear the SID bits in the DEBUG_SID_HALT_REG register, so it will not carry
the old value.  Consider a case where doing ecats with sid = 7 in first
iteration and then sid = 0 in the second iteration. The existing code still
trigger a transaction with sid = 7 as we are not masking off the respective
bits.

Change-Id: Ib646533ec7a986ef541275ef95bc089111d5e335
Signed-off-by: default avatarCharan Teja Reddy <charante@codeaurora.org>
Signed-off-by: default avatarPrakash Gupta <guptap@codeaurora.org>
parent 6a56d6a5

drivers/iommu/arm-smmu.c

+4 −0
Original line number Diff line number Diff line
@@ -5317,6 +5317,7 @@ static phys_addr_t qsmmuv500_iova_to_phys( 
redo:

	/* Set address and stream-id */

	val = readq_relaxed(tbu->base + DEBUG_SID_HALT_REG);

	val &= ~DEBUG_SID_HALT_SID_MASK;

	val |= sid & DEBUG_SID_HALT_SID_MASK;

	writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);

	writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG);
@@ -5379,6 +5380,9 @@ static phys_addr_t qsmmuv500_iova_to_phys( 
	/* Reset hardware */

	writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG);

	writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG);

	val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG);

	val &= ~DEBUG_SID_HALT_SID_MASK;

	writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);



	/*

	 * After a failed translation, the next successful translation will