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Commit d96954a8 authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

ARM: dts: msm: Add DLCT CTI for SDM855 



Add DLCT CTI0 and CTI1 node in SDM855 device tree.

Change-Id: I605d27b6c1659979b54256230cee44a0bceee7e6
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 0ba27bd6

arch/arm64/boot/dts/qcom/sdm855-coresight.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -1702,6 +1702,30 @@ 
		clock-names = "apb_pclk";

	};



	cti0_dlct: cti@6c29000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c29000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-dlct_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_dlct: cti@6c2a000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c2a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-dlct_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti0: cti@6010000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;