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Commit d9408cef authored by Adrian Bunk's avatar Adrian Bunk Committed by Andi Kleen
Browse files

[PATCH] i386: Clean up smp_tune_scheduling() 



- remove the write-only local variable "bandwidth"
- don't set "max_cache_size" in the (cachesize < 0) case:
  that's already handled in kernel/sched.c:measure_migration_cost()

Signed-off-by: default avatarAdrian Bunk <bunk@stusta.de>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Acked-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
parent b65780e1

arch/i386/kernel/smpboot.c

+5 −24
Original line number Original line Diff line number Diff line
@@ -1133,30 +1133,11 @@ static int __cpuinit __smp_prepare_cpu(int cpu) 
static void smp_tune_scheduling(void)

static void smp_tune_scheduling(void)

{

{

	unsigned long cachesize;       /* kB   */

	unsigned long cachesize;       /* kB   */

	unsigned long bandwidth = 350; /* MB/s */

	/*

	 * Rough estimation for SMP scheduling, this is the number of

	 * cycles it takes for a fully memory-limited process to flush

	 * the SMP-local cache.

	 *

	 * (For a P5 this pretty much means we will choose another idle

	 *  CPU almost always at wakeup time (this is due to the small

	 *  L1 cache), on PIIs it's around 50-100 usecs, depending on

	 *  the cache size)

	 */





	if (!cpu_khz) {

	if (cpu_khz) {

		/*

		 * this basically disables processor-affinity

		 * scheduling on SMP without a TSC.

		 */

		return;

	} else {

		cachesize = boot_cpu_data.x86_cache_size;

		cachesize = boot_cpu_data.x86_cache_size;

		if (cachesize == -1) {



			cachesize = 16; /* Pentiums, 2x8kB cache */

		if (cachesize > 0)

			bandwidth = 100;

		}

			max_cache_size = cachesize * 1024;

			max_cache_size = cachesize * 1024;

	}

	}

}

}