Loading arch/arm64/boot/dts/qcom/qcs405.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -283,7 +283,7 @@ }; dcc: dcc_v2@b2000 { compatible = "qcom,dcc_v2"; compatible = "qcom,dcc-v2"; reg = <0x000b2000 0x1000>, <0x000bf800 0x800>; reg-names = "dcc-base", "dcc-ram-base"; Loading arch/arm64/boot/dts/qcom/sm8150.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -2883,7 +2883,7 @@ }; dcc: dcc_v2@10a2000 { compatible = "qcom,dcc_v2"; compatible = "qcom,dcc-v2"; reg = <0x10a2000 0x1000>, <0x10ae000 0x2000>; reg-names = "dcc-base", "dcc-ram-base"; Loading Loading
arch/arm64/boot/dts/qcom/qcs405.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -283,7 +283,7 @@ }; dcc: dcc_v2@b2000 { compatible = "qcom,dcc_v2"; compatible = "qcom,dcc-v2"; reg = <0x000b2000 0x1000>, <0x000bf800 0x800>; reg-names = "dcc-base", "dcc-ram-base"; Loading
arch/arm64/boot/dts/qcom/sm8150.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -2883,7 +2883,7 @@ }; dcc: dcc_v2@10a2000 { compatible = "qcom,dcc_v2"; compatible = "qcom,dcc-v2"; reg = <0x10a2000 0x1000>, <0x10ae000 0x2000>; reg-names = "dcc-base", "dcc-ram-base"; Loading