Loading arch/sparc64/kernel/entry.h +27 −0 Original line number Diff line number Diff line Loading @@ -153,4 +153,31 @@ struct cheetah_err_info { */ extern struct cheetah_err_info *cheetah_error_log; /* UPA nodes send interrupt packet to UltraSparc with first data reg * value low 5 (7 on Starfire) bits holding the IRQ identifier being * delivered. We must translate this into a non-vector IRQ so we can * set the softint on this cpu. * * To make processing these packets efficient and race free we use * an array of irq buckets below. The interrupt vector handler in * entry.S feeds incoming packets into per-cpu pil-indexed lists. * * If you make changes to ino_bucket, please update hand coded assembler * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S */ struct ino_bucket { /*0x00*/unsigned long __irq_chain_pa; /* Virtual interrupt number assigned to this INO. */ /*0x08*/unsigned int __virt_irq; /*0x0c*/unsigned int __pad; }; extern struct ino_bucket *ivector_table; extern unsigned long ivector_table_pa; extern void handler_irq(int irq, struct pt_regs *regs); extern void init_irqwork_curcpu(void); extern void __cpuinit sun4v_register_mondo_queues(int this_cpu); #endif /* _ENTRY_H */ arch/sparc64/kernel/irq.c +2 −19 Original line number Diff line number Diff line Loading @@ -44,27 +44,10 @@ #include <asm/hypervisor.h> #include <asm/cacheflush.h> /* UPA nodes send interrupt packet to UltraSparc with first data reg * value low 5 (7 on Starfire) bits holding the IRQ identifier being * delivered. We must translate this into a non-vector IRQ so we can * set the softint on this cpu. * * To make processing these packets efficient and race free we use * an array of irq buckets below. The interrupt vector handler in * entry.S feeds incoming packets into per-cpu pil-indexed lists. * * If you make changes to ino_bucket, please update hand coded assembler * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S */ struct ino_bucket { /*0x00*/unsigned long __irq_chain_pa; /* Virtual interrupt number assigned to this INO. */ /*0x08*/unsigned int __virt_irq; /*0x0c*/unsigned int __pad; }; #include "entry.h" #define NUM_IVECS (IMAP_INR + 1) struct ino_bucket *ivector_table; unsigned long ivector_table_pa; Loading include/asm-sparc64/irq.h +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ extern unsigned char virt_irq_alloc(unsigned int dev_handle, extern void virt_irq_free(unsigned int virt_irq); #endif extern void __init init_IRQ(void); extern void fixup_irqs(void); static inline void set_softint(unsigned long bits) Loading Loading
arch/sparc64/kernel/entry.h +27 −0 Original line number Diff line number Diff line Loading @@ -153,4 +153,31 @@ struct cheetah_err_info { */ extern struct cheetah_err_info *cheetah_error_log; /* UPA nodes send interrupt packet to UltraSparc with first data reg * value low 5 (7 on Starfire) bits holding the IRQ identifier being * delivered. We must translate this into a non-vector IRQ so we can * set the softint on this cpu. * * To make processing these packets efficient and race free we use * an array of irq buckets below. The interrupt vector handler in * entry.S feeds incoming packets into per-cpu pil-indexed lists. * * If you make changes to ino_bucket, please update hand coded assembler * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S */ struct ino_bucket { /*0x00*/unsigned long __irq_chain_pa; /* Virtual interrupt number assigned to this INO. */ /*0x08*/unsigned int __virt_irq; /*0x0c*/unsigned int __pad; }; extern struct ino_bucket *ivector_table; extern unsigned long ivector_table_pa; extern void handler_irq(int irq, struct pt_regs *regs); extern void init_irqwork_curcpu(void); extern void __cpuinit sun4v_register_mondo_queues(int this_cpu); #endif /* _ENTRY_H */
arch/sparc64/kernel/irq.c +2 −19 Original line number Diff line number Diff line Loading @@ -44,27 +44,10 @@ #include <asm/hypervisor.h> #include <asm/cacheflush.h> /* UPA nodes send interrupt packet to UltraSparc with first data reg * value low 5 (7 on Starfire) bits holding the IRQ identifier being * delivered. We must translate this into a non-vector IRQ so we can * set the softint on this cpu. * * To make processing these packets efficient and race free we use * an array of irq buckets below. The interrupt vector handler in * entry.S feeds incoming packets into per-cpu pil-indexed lists. * * If you make changes to ino_bucket, please update hand coded assembler * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S */ struct ino_bucket { /*0x00*/unsigned long __irq_chain_pa; /* Virtual interrupt number assigned to this INO. */ /*0x08*/unsigned int __virt_irq; /*0x0c*/unsigned int __pad; }; #include "entry.h" #define NUM_IVECS (IMAP_INR + 1) struct ino_bucket *ivector_table; unsigned long ivector_table_pa; Loading
include/asm-sparc64/irq.h +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ extern unsigned char virt_irq_alloc(unsigned int dev_handle, extern void virt_irq_free(unsigned int virt_irq); #endif extern void __init init_IRQ(void); extern void fixup_irqs(void); static inline void set_softint(unsigned long bits) Loading
David S. Miller <davem@davemloft.net>David S. Miller <davem@davemloft.net>