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Commit d8fce2db authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "Mostly tooling fixes, but also an uncore PMU driver fix and an uncore
  PMU driver hardware-enablement addition"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf probe: Fix segfault if passed with ''.
  perf report: Fix -T/--threads option to work again
  perf bench numa: Fix immediate meeting of convergence condition
  perf bench numa: Fixes of --quiet argument
  perf bench futex: Fix hung wakeup tasks after requeueing
  perf probe: Fix bug with global variables handling
  perf top: Fix a segfault when kernel map is restricted.
  tools lib traceevent: Fix build failure on 32-bit arch
  perf kmem: Fix compiles on RHEL6/OL6
  tools lib api: Undefine _FORTIFY_SOURCE before setting it
  perf kmem: Consistently use PRIu64 for printing u64 values
  perf trace: Disable events and drain events when forked workload ends
  perf trace: Enable events when doing system wide tracing and starting a workload
  perf/x86/intel/uncore: Move PCI IDs for IMC to uncore driver
  perf/x86/intel/uncore: Add support for Intel Haswell ULT (lower power Mobile Processor) IMC uncore PMUs
  perf/x86/intel: Add cpu_(prepare|starting|dying) for core_pmu
parents 02f0f572 74f40c1f

arch/x86/kernel/cpu/perf_event_intel.c

+38 −28
Original line number Original line Diff line number Diff line
@@ -2533,34 +2533,6 @@ ssize_t intel_event_sysfs_show(char *page, u64 config) 
	return x86_event_sysfs_show(page, config, event);

	return x86_event_sysfs_show(page, config, event);

}

}





static __initconst const struct x86_pmu core_pmu = {

	.name			= "core",

	.handle_irq		= x86_pmu_handle_irq,

	.disable_all		= x86_pmu_disable_all,

	.enable_all		= core_pmu_enable_all,

	.enable			= core_pmu_enable_event,

	.disable		= x86_pmu_disable_event,

	.hw_config		= x86_pmu_hw_config,

	.schedule_events	= x86_schedule_events,

	.eventsel		= MSR_ARCH_PERFMON_EVENTSEL0,

	.perfctr		= MSR_ARCH_PERFMON_PERFCTR0,

	.event_map		= intel_pmu_event_map,

	.max_events		= ARRAY_SIZE(intel_perfmon_event_map),

	.apic			= 1,

	/*

	 * Intel PMCs cannot be accessed sanely above 32 bit width,

	 * so we install an artificial 1<<31 period regardless of

	 * the generic event period:

	 */

	.max_period		= (1ULL << 31) - 1,

	.get_event_constraints	= intel_get_event_constraints,

	.put_event_constraints	= intel_put_event_constraints,

	.event_constraints	= intel_core_event_constraints,

	.guest_get_msrs		= core_guest_get_msrs,

	.format_attrs		= intel_arch_formats_attr,

	.events_sysfs_show	= intel_event_sysfs_show,

};



struct intel_shared_regs *allocate_shared_regs(int cpu)

struct intel_shared_regs *allocate_shared_regs(int cpu)

{

{

	struct intel_shared_regs *regs;

	struct intel_shared_regs *regs;
@@ -2743,6 +2715,44 @@ static struct attribute *intel_arch3_formats_attr[] = { 
	NULL,

	NULL,

};

};





static __initconst const struct x86_pmu core_pmu = {

	.name			= "core",

	.handle_irq		= x86_pmu_handle_irq,

	.disable_all		= x86_pmu_disable_all,

	.enable_all		= core_pmu_enable_all,

	.enable			= core_pmu_enable_event,

	.disable		= x86_pmu_disable_event,

	.hw_config		= x86_pmu_hw_config,

	.schedule_events	= x86_schedule_events,

	.eventsel		= MSR_ARCH_PERFMON_EVENTSEL0,

	.perfctr		= MSR_ARCH_PERFMON_PERFCTR0,

	.event_map		= intel_pmu_event_map,

	.max_events		= ARRAY_SIZE(intel_perfmon_event_map),

	.apic			= 1,

	/*

	 * Intel PMCs cannot be accessed sanely above 32-bit width,

	 * so we install an artificial 1<<31 period regardless of

	 * the generic event period:

	 */

	.max_period		= (1ULL<<31) - 1,

	.get_event_constraints	= intel_get_event_constraints,

	.put_event_constraints	= intel_put_event_constraints,

	.event_constraints	= intel_core_event_constraints,

	.guest_get_msrs		= core_guest_get_msrs,

	.format_attrs		= intel_arch_formats_attr,

	.events_sysfs_show	= intel_event_sysfs_show,



	/*

	 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs

	 * together with PMU version 1 and thus be using core_pmu with

	 * shared_regs. We need following callbacks here to allocate

	 * it properly.

	 */

	.cpu_prepare		= intel_pmu_cpu_prepare,

	.cpu_starting		= intel_pmu_cpu_starting,

	.cpu_dying		= intel_pmu_cpu_dying,

};



static __initconst const struct x86_pmu intel_pmu = {

static __initconst const struct x86_pmu intel_pmu = {

	.name			= "Intel",

	.name			= "Intel",

	.handle_irq		= intel_pmu_handle_irq,

	.handle_irq		= intel_pmu_handle_irq,

arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c

+12 −0
Original line number Original line Diff line number Diff line 
/* Nehalem/SandBridge/Haswell uncore support */

/* Nehalem/SandBridge/Haswell uncore support */

#include "perf_event_intel_uncore.h"

#include "perf_event_intel_uncore.h"





/* Uncore IMC PCI IDs */

#define PCI_DEVICE_ID_INTEL_SNB_IMC	0x0100

#define PCI_DEVICE_ID_INTEL_IVB_IMC	0x0154

#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC	0x0150

#define PCI_DEVICE_ID_INTEL_HSW_IMC	0x0c00

#define PCI_DEVICE_ID_INTEL_HSW_U_IMC	0x0a04



/* SNB event control */

/* SNB event control */

#define SNB_UNC_CTL_EV_SEL_MASK			0x000000ff

#define SNB_UNC_CTL_EV_SEL_MASK			0x000000ff

#define SNB_UNC_CTL_UMASK_MASK			0x0000ff00

#define SNB_UNC_CTL_UMASK_MASK			0x0000ff00
@@ -472,6 +479,10 @@ static const struct pci_device_id hsw_uncore_pci_ids[] = { 
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	},

	{ /* IMC */

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* end: all zeroes */ },

	{ /* end: all zeroes */ },

};

};
@@ -502,6 +513,7 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = { 
	IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */

	IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */

	IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */

	IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */

	IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */

	IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */

	IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */

	{  /* end marker */ }

	{  /* end marker */ }

};

};

include/linux/pci_ids.h

+0 −4
Original line number Original line Diff line number Diff line
@@ -2541,10 +2541,6 @@ 




#define PCI_VENDOR_ID_INTEL		0x8086

#define PCI_VENDOR_ID_INTEL		0x8086

#define PCI_DEVICE_ID_INTEL_EESSC	0x0008

#define PCI_DEVICE_ID_INTEL_EESSC	0x0008

#define PCI_DEVICE_ID_INTEL_SNB_IMC	0x0100

#define PCI_DEVICE_ID_INTEL_IVB_IMC	0x0154

#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC	0x0150

#define PCI_DEVICE_ID_INTEL_HSW_IMC	0x0c00

#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320

#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320

#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321

#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321

#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329

#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329

tools/lib/api/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -16,7 +16,7 @@ MAKEFLAGS += --no-print-directory 
LIBFILE = $(OUTPUT)libapi.a

LIBFILE = $(OUTPUT)libapi.a





CFLAGS := $(EXTRA_WARNINGS) $(EXTRA_CFLAGS)

CFLAGS := $(EXTRA_WARNINGS) $(EXTRA_CFLAGS)

CFLAGS += -ggdb3 -Wall -Wextra -std=gnu99 -Werror -O6 -D_FORTIFY_SOURCE=2 -fPIC

CFLAGS += -ggdb3 -Wall -Wextra -std=gnu99 -Werror -O6 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -fPIC

CFLAGS += -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64

CFLAGS += -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64





RM = rm -f

RM = rm -f

tools/lib/traceevent/event-parse.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -3865,7 +3865,7 @@ static void print_str_arg(struct trace_seq *s, void *data, int size, 
			} else if (el_size == 4) {

			} else if (el_size == 4) {

				trace_seq_printf(s, "%u", *(uint32_t *)num);

				trace_seq_printf(s, "%u", *(uint32_t *)num);

			} else if (el_size == 8) {

			} else if (el_size == 8) {

				trace_seq_printf(s, "%lu", *(uint64_t *)num);

				trace_seq_printf(s, "%"PRIu64, *(uint64_t *)num);

			} else {

			} else {

				trace_seq_printf(s, "BAD SIZE:%d 0x%x",

				trace_seq_printf(s, "BAD SIZE:%d 0x%x",

						 el_size, *(uint8_t *)num);

						 el_size, *(uint8_t *)num);