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Commit d8fca2c2 authored by Taniya Das's avatar Taniya Das Committed by Shefali Jain
Browse files

clk: qcom: Add support for GPUCC driver 



Add graphics clock controller driver for SDMMAGPIE
for the client to be able to perform clock operations.

Change-Id: I833595a6dd3b4ef3922550bb2be8cb2d9993af69
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent dcb40bc8

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+2 −1
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ Required properties : 
- compatible : shall contain one of the following:

		"qcom,gpucc-sm8150",

		"qcom,gpucc-sdmshrike",

		"qcom,gpucc-sm6150".

		"qcom,gpucc-sm6150",

		"qcom,gpucc-sdmmagpie".



- reg : shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

drivers/clk/qcom/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -431,3 +431,11 @@ config MSM_NPUCC_SDMMAGPIE 
          Support for the NPU clock controller on Qualcomm Technologies, Inc

	  SDMMAGPIE devices.

	  Say Y if you want to enable use of the Network Processing Unit.



config MSM_GPUCC_SDMMAGPIE

	tristate "SDMMAGPIE graphics Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the graphics clock controller on Qualcomm Technologies, Inc.

	  SDMMAGPIE devices.

	  Say Y if you want to support graphics clocks.

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ obj-$(CONFIG_MSM_GCC_SM6150) += gcc-sm6150.o 
obj-$(CONFIG_MSM_GCC_SM8150) += gcc-sm8150.o

obj-$(CONFIG_MSM_GCC_SDMMAGPIE) += gcc-sdmmagpie.o

obj-$(CONFIG_MSM_GCC_SDMSHRIKE) += gcc-sdmshrike.o

obj-$(CONFIG_MSM_GPUCC_SDMMAGPIE) += gpucc-sdmmagpie.o

obj-$(CONFIG_MSM_GPUCC_SM6150) += gpucc-sm6150.o

obj-$(CONFIG_MSM_GPUCC_SM8150) += gpucc-sm8150.o

obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o

drivers/clk/qcom/gpucc-sdmmagpie.c

0 → 100644
+596 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#define pr_fmt(fmt) "clk: %s: " fmt, __func__



#include <linux/kernel.h>

#include <linux/err.h>

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <linux/reset-controller.h>



#include <dt-bindings/clock/qcom,gpucc-sdmmagpie.h>



#include "clk-alpha-pll.h"

#include "clk-branch.h"

#include "clk-pll.h"

#include "clk-rcg.h"

#include "clk-regmap.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



enum vdd_gx_levels {

	VDD_GX_NONE,

	VDD_GX_MIN,		/* MIN SVS */

	VDD_GX_LOWER,		/* SVS2 */

	VDD_GX_LOW,		/* SVS */

	VDD_GX_LOW_L1,		/* SVSL1 */

	VDD_GX_NOMINAL,		/* NOM */

	VDD_GX_NOMINAL_L1,	/* NOM1 */

	VDD_GX_HIGH,		/* TURBO */

	VDD_GX_HIGH_L1,		/* TURBO1 */

	VDD_GX_NUM,

};



static int vdd_gx_corner[] = {

	RPMH_REGULATOR_LEVEL_OFF,		/* VDD_GX_NONE */

	RPMH_REGULATOR_LEVEL_MIN_SVS,		/* VDD_GX_MIN */

	RPMH_REGULATOR_LEVEL_LOW_SVS,		/* VDD_GX_LOWER */

	RPMH_REGULATOR_LEVEL_SVS,		/* VDD_GX_LOW */

	RPMH_REGULATOR_LEVEL_SVS_L1,		/* VDD_GX_LOW_L1 */

	RPMH_REGULATOR_LEVEL_NOM,		/* VDD_GX_NOMINAL */

	RPMH_REGULATOR_LEVEL_NOM_L1,		/* VDD_GX_NOMINAL_L1 */

	RPMH_REGULATOR_LEVEL_TURBO,		/* VDD_GX_HIGH */

	RPMH_REGULATOR_LEVEL_TURBO_L1,		/* VDD_GX_HIGH_L1 */

	RPMH_REGULATOR_LEVEL_MAX,		/* VDD_GX_MAX */

};



static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_gx, VDD_GX_NUM, 1, vdd_gx_corner);



#define CX_GMU_CBCR_SLEEP_MASK		0xF

#define CX_GMU_CBCR_SLEEP_SHIFT		4

#define CX_GMU_CBCR_WAKE_MASK		0xF

#define CX_GMU_CBCR_WAKE_SHIFT		8



enum {

	P_BI_TCXO,

	P_CORE_BI_PLL_TEST_SE,

	P_GPLL0_OUT_MAIN,

	P_GPLL0_OUT_MAIN_DIV,

	P_GPU_CC_PLL0_OUT_EVEN,

	P_GPU_CC_PLL0_OUT_MAIN,

	P_GPU_CC_PLL0_OUT_ODD,

	P_GPU_CC_PLL1_OUT_EVEN,

	P_GPU_CC_PLL1_OUT_MAIN,

	P_GPU_CC_PLL1_OUT_ODD,

};



static const struct parent_map gpu_cc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },

	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_MAIN_DIV, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gpu_cc_parent_names_0[] = {

	"bi_tcxo",

	"gpu_cc_pll0",

	"gpu_cc_pll1",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};



static const struct parent_map gpu_cc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPU_CC_PLL0_OUT_EVEN, 1 },

	{ P_GPU_CC_PLL0_OUT_ODD, 2 },

	{ P_GPU_CC_PLL1_OUT_EVEN, 3 },

	{ P_GPU_CC_PLL1_OUT_ODD, 4 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gpu_cc_parent_names_1[] = {

	"bi_tcxo",

	"gpu_cc_pll0_out_even",

	"gpu_cc_pll0_out_odd",

	"gpu_cc_pll1_out_even",

	"gpu_cc_pll1_out_odd",

	"gcc_gpu_gpll0_clk_src",

	"core_bi_pll_test_se",

};



static struct pll_vco fabia_vco[] = {

	{ 249600000, 2000000000, 0 },

	{ 125000000, 1000000000, 1 },

};



static const struct alpha_pll_config gpu_cc_pll0_config = {

	.l = 0x12,

	.alpha = 0xC000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002067,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00004805,

	.test_ctl_hi_val = 0x40000000,

};



static struct clk_alpha_pll gpu_cc_pll0 = {

	.offset = 0x0,

	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_pll0",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_fabia_pll_ops,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static const struct clk_div_table post_div_table_fabia_even[] = {

	{ 0x0, 1 },

	{ 0x1, 2 },

	{ 0x3, 4 },

	{ 0x7, 8 },

	{ }

};



static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {

	.offset = 0x0,

	.post_div_shift = 8,

	.post_div_table = post_div_table_fabia_even,

	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),

	.width = 4,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_pll0_out_even",

		.parent_names = (const char *[]){ "gpu_cc_pll0" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_generic_pll_postdiv_ops,

	},

};



static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_gmu_clk_src = {

	.cmd_rcgr = 0x1120,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gpu_cc_parent_map_0,

	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_gmu_clk_src",

		.parent_names = gpu_cc_parent_names_0,

		.num_parents = 6,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 200000000},

	},

};



/* PLL would be 2 times. */

static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {

	F(180000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(267000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(780000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {

	.cmd_rcgr = 0x101c,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gpu_cc_parent_map_1,

	.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,

	.flags = FORCE_ENABLE_RCG,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_gx_gfx3d_clk_src",

		.parent_names = gpu_cc_parent_names_1,

		.num_parents = 7,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_gx,

		.num_rate_max = VDD_GX_NUM,

		.rate_max = (unsigned long[VDD_GX_NUM]) {

			[VDD_GX_MIN] = 180000000,

			[VDD_GX_LOWER] = 267000000,

			[VDD_GX_LOW] = 355000000,

			[VDD_GX_LOW_L1] = 430000000,

			[VDD_GX_NOMINAL] = 565000000,

			[VDD_GX_NOMINAL_L1] = 650000000,

			[VDD_GX_HIGH] = 750000000,

			[VDD_GX_HIGH_L1] = 780000000},

	},

};



static struct clk_branch gpu_cc_acd_ahb_clk = {

	.halt_reg = 0x1168,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1168,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_acd_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_acd_cxo_clk = {

	.halt_reg = 0x1164,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1164,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_acd_cxo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_ahb_clk = {

	.halt_reg = 0x1078,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1078,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_crc_ahb_clk = {

	.halt_reg = 0x107c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x107c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_crc_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_apb_clk = {

	.halt_reg = 0x1088,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x1088,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_apb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_gfx3d_clk = {

	.halt_reg = 0x10a4,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x10a4,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gfx3d_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gx_gfx3d_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {

	.halt_reg = 0x10a8,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x10a8,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gfx3d_slv_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gx_gfx3d_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_gmu_clk = {

	.halt_reg = 0x1098,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1098,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gmu_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gmu_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {

	.halt_reg = 0x108c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x108c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_snoc_dvm_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cxo_aon_clk = {

	.halt_reg = 0x1004,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x1004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cxo_aon_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cxo_clk = {

	.halt_reg = 0x109c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x109c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cxo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_gx_cxo_clk = {

	.halt_reg = 0x1060,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1060,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_gx_cxo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_gx_gfx3d_clk = {

	.halt_reg = 0x1054,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1054,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_gx_gfx3d_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gx_gfx3d_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_gx_gmu_clk = {

	.halt_reg = 0x1064,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1064,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_gx_gmu_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gmu_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_gx_vsense_clk = {

	.halt_reg = 0x1058,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x1058,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_gx_vsense_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_regmap *gpu_cc_sdmmagpie_clocks[] = {

	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,

	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,

	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,

	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,

	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,

	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,

	[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,

	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,

	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,

	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,

	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,

	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,

	[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,

	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,

	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,

	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,

	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,

	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,

	[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,

};



static const struct regmap_config gpu_cc_sdmmagpie_regmap_config = {

	.reg_bits	= 32,

	.reg_stride	= 4,

	.val_bits	= 32,

	.max_register	= 0x8008,

	.fast_io	= true,

};



static const struct qcom_cc_desc gpu_cc_sdmmagpie_desc = {

	.config = &gpu_cc_sdmmagpie_regmap_config,

	.clks = gpu_cc_sdmmagpie_clocks,

	.num_clks = ARRAY_SIZE(gpu_cc_sdmmagpie_clocks),

};



static const struct of_device_id gpu_cc_sdmmagpie_match_table[] = {

	{ .compatible = "qcom,gpucc-sdmmagpie" },

	{ }

};

MODULE_DEVICE_TABLE(of, gpu_cc_sdmmagpie_match_table);



static int gpu_cc_sdmmagpie_probe(struct platform_device *pdev)

{

	struct regmap *regmap;

	int ret;

	unsigned int value, mask;



	/* Get CX voltage regulator for CX and GMU clocks. */

	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");

	if (IS_ERR(vdd_cx.regulator[0])) {

		if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_cx regulator\n");

		return PTR_ERR(vdd_cx.regulator[0]);

	}



	/* Get MX voltage regulator for GPU PLL graphic clock. */

	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");

	if (IS_ERR(vdd_mx.regulator[0])) {

		if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_mx regulator\n");

		return PTR_ERR(vdd_mx.regulator[0]);

	}



	/* GFX voltage regulators for GFX3D  graphic clock. */

	vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx");

	if (IS_ERR(vdd_gx.regulator[0])) {

		if (PTR_ERR(vdd_gx.regulator[0]) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");

		return PTR_ERR(vdd_gx.regulator[0]);

	}



	/* Avoid turning on the rail during clock registration */

	vdd_gx.skip_handoff = true;



	regmap = qcom_cc_map(pdev, &gpu_cc_sdmmagpie_desc);

	if (IS_ERR(regmap)) {

		pr_err("Failed to map the gpu_cc registers\n");

		return PTR_ERR(regmap);

	}



	clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sdmmagpie_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");

		return ret;

	}



	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */

	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;

	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;

	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;

	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,

								mask, value);



	dev_info(&pdev->dev, "Registered GPU CC clocks\n");



	return ret;

}



static struct platform_driver gpu_cc_sdmmagpie_driver = {

	.probe = gpu_cc_sdmmagpie_probe,

	.driver = {

		.name = "gpu_cc-sdmmagpie",

		.of_match_table = gpu_cc_sdmmagpie_match_table,

	},

};



static int __init gpu_cc_sdmmagpie_init(void)

{

	return platform_driver_register(&gpu_cc_sdmmagpie_driver);

}

subsys_initcall(gpu_cc_sdmmagpie_init);



static void __exit gpu_cc_sdmmagpie_exit(void)

{

	platform_driver_unregister(&gpu_cc_sdmmagpie_driver);

}

module_exit(gpu_cc_sdmmagpie_exit);



MODULE_DESCRIPTION("QTI GPU_CC SDMMAGPIE Driver");

MODULE_LICENSE("GPL v2");

MODULE_ALIAS("platform:gpu_cc-sdmmagpie");

include/dt-bindings/clock/qcom,gpucc-sdmmagpie.h

+19 −22
Original line number Diff line number Diff line
@@ -14,28 +14,25 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SDMMAGPIE_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SDMMAGPIE_H



#define GPU_CC_ACD_AHB_CLK					0

#define GPU_CC_ACD_CXO_CLK					1

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CRC_AHB_CLK					3

#define GPU_CC_CX_APB_CLK					4

#define GPU_CC_CX_GFX3D_CLK					5

#define GPU_CC_CX_GFX3D_SLV_CLK					6

#define GPU_CC_CX_GMU_CLK					7

#define GPU_CC_CX_SNOC_DVM_CLK					8

#define GPU_CC_CXO_AON_CLK					9

#define GPU_CC_CXO_CLK						10

#define GPU_CC_GMU_CLK_SRC					11

#define GPU_CC_GX_CXO_CLK					12

#define GPU_CC_GX_GFX3D_CLK					13

#define GPU_CC_GX_GFX3D_CLK_SRC					14

#define GPU_CC_GX_GMU_CLK					15

#define GPU_CC_GX_VSENSE_CLK					16

#define GPU_CC_PLL0						17

#define GPU_CC_PLL0_OUT_EVEN					18

#define GPU_CC_PLL0						0

#define GPU_CC_PLL0_OUT_EVEN					1

#define GPU_CC_ACD_AHB_CLK					2

#define GPU_CC_ACD_CXO_CLK					3

#define GPU_CC_AHB_CLK						4

#define GPU_CC_CRC_AHB_CLK					5

#define GPU_CC_CX_APB_CLK					6

#define GPU_CC_CX_GFX3D_CLK					7

#define GPU_CC_CX_GFX3D_SLV_CLK					8

#define GPU_CC_CX_GMU_CLK					9

#define GPU_CC_CX_SNOC_DVM_CLK					10

#define GPU_CC_CXO_AON_CLK					11

#define GPU_CC_CXO_CLK						12

#define GPU_CC_GMU_CLK_SRC					13

#define GPU_CC_GX_CXO_CLK					14

#define GPU_CC_GX_GFX3D_CLK					15

#define GPU_CC_GX_GFX3D_CLK_SRC					16

#define GPU_CC_GX_GMU_CLK					17

#define GPU_CC_GX_VSENSE_CLK					18

#define GPU_CC_SLEEP_CLK					19



#define CX_GDSC							0

#define GX_GDSC							1



#endif